📄 monitor.rpt
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Project Information e:\ajun\monitor.rpt
MAX+plus II Compiler Report File
Version 9.3 7/23/1999
Compiled: 04/24/2009 23:21:25
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MONITOR
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
monitor EPM7128SLC84-15 9 21 0 21 0 16 %
User Pins: 9 21 0
Device-Specific Information: e:\ajun\monitor.rpt
monitor
***** Logic for device 'monitor' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R
E
V S
C E V
S C R C
I G I G G G G G V Y Y C Y Y Y
G A A A N A A A N N N N N N E 0 0 I 0 0 0
N 7 6 4 D 3 2 1 T D D D D D D 6 5 O 4 2 0
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
A0 | 12 74 | Y03
VCCIO | 13 73 | Y01
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
RESERVED | 16 70 | Y11
RESERVED | 17 69 | Y16
RESERVED | 18 68 | Y15
GND | 19 67 | Y14
RESERVED | 20 66 | VCCIO
A5 | 21 65 | Y13
RESERVED | 22 EPM7128SLC84-15 64 | Y12
#TMS | 23 63 | Y10
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | S0
VCCIO | 26 60 | S6
RESERVED | 27 59 | GND
RESERVED | 28 58 | S1
RESERVED | 29 57 | S5
RESERVED | 30 56 | S2
RESERVED | 31 55 | S4
GND | 32 54 | S3
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R R V R R R G V R R R G R R R R R V
E E E E E C E E E N C E E E N E E E E E C
S S S S S C S S S D C S S S D S S S S S C
E E E E E I E E E I E E E E E E E E I
R R R R R O R R R N R R R R R R R R O
V V V V V V V V T V V V V V V V V
E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\ajun\monitor.rpt
monitor
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 2/ 8( 25%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 7/16( 43%) 8/ 8(100%) 0/16( 0%) 1/36( 2%)
G: LC97 - LC112 7/16( 43%) 8/ 8(100%) 2/16( 12%) 4/36( 11%)
H: LC113 - LC128 7/16( 43%) 7/ 8( 87%) 2/16( 12%) 4/36( 11%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 34/64 ( 53%)
Total logic cells used: 21/128 ( 16%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 21/128 ( 16%)
Total shareable expanders not available (n/a): 4/128 ( 3%)
Average fan-in: 3.00
Total fan-in: 63
Total input pins required: 9
Total fast input logic cells required: 0
Total output pins required: 21
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 21
Total flipflops required: 0
Total product terms required: 65
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: e:\ajun\monitor.rpt
monitor
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
12 (3) (A) INPUT 0 0 0 0 0 7 0 A0
4 (16) (A) INPUT 0 0 0 0 0 7 0 A1
5 (14) (A) INPUT 0 0 0 0 0 7 0 A2
6 (13) (A) INPUT 0 0 0 0 0 7 0 A3
8 (11) (A) INPUT 0 0 0 0 0 7 0 A4
21 (19) (B) INPUT 0 0 0 0 0 7 0 A5
9 (8) (A) INPUT 0 0 0 0 0 7 0 A6
10 (6) (A) INPUT 0 0 0 0 0 7 0 A7
11 (5) (A) INPUT 0 0 0 0 0 7 0 SIGN
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\ajun\monitor.rpt
monitor
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
61 94 F OUTPUT t 0 0 0 1 0 0 0 S0
58 91 F OUTPUT t 0 0 0 1 0 0 0 S1
56 86 F OUTPUT t 0 0 0 1 0 0 0 S2
54 83 F OUTPUT t 0 0 0 1 0 0 0 S3
55 85 F OUTPUT t 0 0 0 1 0 0 0 S4
57 88 F OUTPUT t 0 0 0 1 0 0 0 S5
60 93 F OUTPUT t 0 0 0 1 0 0 0 S6
75 118 H OUTPUT t 0 0 0 4 0 0 0 Y00
73 115 H OUTPUT t 1 0 1 4 0 0 0 Y01
76 120 H OUTPUT t 0 0 0 4 0 0 0 Y02
74 117 H OUTPUT t 0 0 0 4 0 0 0 Y03
77 123 H OUTPUT t 0 0 0 4 0 0 0 Y04
79 125 H OUTPUT t 1 0 1 4 0 0 0 Y05
80 126 H OUTPUT t 0 0 0 4 0 0 0 Y06
63 97 G OUTPUT t 0 0 0 4 0 0 0 Y10
70 109 G OUTPUT t 1 0 1 4 0 0 0 Y11
64 99 G OUTPUT t 0 0 0 4 0 0 0 Y12
65 101 G OUTPUT t 0 0 0 4 0 0 0 Y13
67 104 G OUTPUT t 0 0 0 4 0 0 0 Y14
68 105 G OUTPUT t 1 0 1 4 0 0 0 Y15
69 107 G OUTPUT t 0 0 0 4 0 0 0 Y16
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\ajun\monitor.rpt
monitor
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+------------- LC94 S0
| +----------- LC91 S1
| | +--------- LC86 S2
| | | +------- LC83 S3
| | | | +----- LC85 S4
| | | | | +--- LC88 S5
| | | | | | +- LC93 S6
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'F'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
11 -> * * * * * * * | - - - - - * - - | <-- SIGN
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ajun\monitor.rpt
monitor
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------- LC97 Y10
| +----------- LC109 Y11
| | +--------- LC99 Y12
| | | +------- LC101 Y13
| | | | +----- LC104 Y14
| | | | | +--- LC105 Y15
| | | | | | +- LC107 Y16
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'G'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
8 -> * * * * * * * | - - - - - - * - | <-- A4
21 -> * * * * * * * | - - - - - - * - | <-- A5
9 -> * * * * * * * | - - - - - - * - | <-- A6
10 -> * * * * * * * | - - - - - - * - | <-- A7
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