📄 putin.rpt
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putin
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----------------------- LC128 XSIGN
| +--------------------- LC125 X0
| | +------------------- LC123 X1
| | | +----------------- LC126 X2
| | | | +--------------- LC118 YSIGN
| | | | | +------------- LC120 Y0
| | | | | | +----------- LC117 Y1
| | | | | | | +--------- LC115 Y2
| | | | | | | | +------- LC113 ~173~1
| | | | | | | | | +----- LC114 ~182~1
| | | | | | | | | | +--- LC116 ~191~1
| | | | | | | | | | | +- LC121 ~200~1
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC118-> - - - - * - - - - - - - | - - - - - - - * | <-- YSIGN
LC120-> - - - - - * - - - - - - | - - - - - - - * | <-- Y0
LC117-> - - - - - - * - - - - - | - - - - - - - * | <-- Y1
LC115-> - - - - - - - * - - - - | - - - - - - - * | <-- Y2
LC113-> - - - * - - - - * - - - | - - - - - - - * | <-- ~173~1
LC114-> - - * - - - - - - * - - | - - - - - - - * | <-- ~182~1
LC116-> - * - - - - - - - - * - | - - - - - - - * | <-- ~191~1
LC121-> * - - - - - - - - - - * | - - - - - - - * | <-- ~200~1
Pin
12 -> * * * * * * * * * * * * | - - - - - - * * | <-- CP0
11 -> - - - - * * * * - - - - | - - - - - - * * | <-- CP1
8 -> - * - - - * - - - - * - | - - - - - - - * | <-- DATA0
6 -> - - * - - - * - - * - - | - - - - - - - * | <-- DATA1
5 -> - - - * - - - * * - - - | - - - - - - - * | <-- DATA2
10 -> * - - - * - - - - - - * | - - - - - - - * | <-- DATA4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\ajun\putin.rpt
putin
** EQUATIONS **
CP0 : INPUT;
CP1 : INPUT;
DATA0 : INPUT;
DATA1 : INPUT;
DATA2 : INPUT;
DATA3 : INPUT;
DATA4 : INPUT;
-- Node name is 'XSIGN'
-- Equation name is 'XSIGN', location is LC128, type is output.
XSIGN = LCELL( _EQ001 $ GND);
_EQ001 = CP0 & DATA4
# !CP0 & _LC121;
-- Node name is 'X0'
-- Equation name is 'X0', location is LC125, type is output.
X0 = LCELL( _EQ002 $ GND);
_EQ002 = CP0 & DATA0
# !CP0 & _LC116;
-- Node name is 'X1'
-- Equation name is 'X1', location is LC123, type is output.
X1 = LCELL( _EQ003 $ GND);
_EQ003 = CP0 & DATA1
# !CP0 & _LC114;
-- Node name is 'X2'
-- Equation name is 'X2', location is LC126, type is output.
X2 = LCELL( _EQ004 $ GND);
_EQ004 = CP0 & DATA2
# !CP0 & _LC113;
-- Node name is 'X3'
-- Equation name is 'X3', location is LC099, type is output.
X3 = LCELL( _EQ005 $ GND);
_EQ005 = CP0 & DATA3
# !CP0 & _LC100;
-- Node name is 'YSIGN' = '~155~1'
-- Equation name is 'YSIGN', location is LC118, type is output.
YSIGN = LCELL( _EQ006 $ GND);
_EQ006 = !CP0 & CP1 & DATA4
# CP0 & YSIGN
# !CP1 & YSIGN
# CP1 & DATA4 & YSIGN
# !CP0 & DATA4 & YSIGN;
-- Node name is 'Y0' = '~146~1'
-- Equation name is 'Y0', location is LC120, type is output.
Y0 = LCELL( _EQ007 $ GND);
_EQ007 = !CP0 & CP1 & DATA0
# CP0 & Y0
# !CP1 & Y0
# CP1 & DATA0 & Y0
# !CP0 & DATA0 & Y0;
-- Node name is 'Y1' = '~137~1'
-- Equation name is 'Y1', location is LC117, type is output.
Y1 = LCELL( _EQ008 $ GND);
_EQ008 = !CP0 & CP1 & DATA1
# CP0 & Y1
# !CP1 & Y1
# CP1 & DATA1 & Y1
# !CP0 & DATA1 & Y1;
-- Node name is 'Y2' = '~128~1'
-- Equation name is 'Y2', location is LC115, type is output.
Y2 = LCELL( _EQ009 $ GND);
_EQ009 = !CP0 & CP1 & DATA2
# CP0 & Y2
# !CP1 & Y2
# CP1 & DATA2 & Y2
# !CP0 & DATA2 & Y2;
-- Node name is 'Y3' = '~119~1'
-- Equation name is 'Y3', location is LC097, type is output.
Y3 = LCELL( _EQ010 $ GND);
_EQ010 = !CP0 & CP1 & DATA3
# CP0 & Y3
# !CP1 & Y3
# CP1 & DATA3 & Y3
# !CP0 & DATA3 & Y3;
-- Node name is '~164~1'
-- Equation name is '~164~1', location is LC100, type is buried.
-- synthesized logic cell
_LC100 = LCELL( _EQ011 $ GND);
_EQ011 = CP0 & DATA3
# !CP0 & _LC100
# DATA3 & _LC100;
-- Node name is '~173~1'
-- Equation name is '~173~1', location is LC113, type is buried.
-- synthesized logic cell
_LC113 = LCELL( _EQ012 $ GND);
_EQ012 = CP0 & DATA2
# !CP0 & _LC113
# DATA2 & _LC113;
-- Node name is '~182~1'
-- Equation name is '~182~1', location is LC114, type is buried.
-- synthesized logic cell
_LC114 = LCELL( _EQ013 $ GND);
_EQ013 = CP0 & DATA1
# !CP0 & _LC114
# DATA1 & _LC114;
-- Node name is '~191~1'
-- Equation name is '~191~1', location is LC116, type is buried.
-- synthesized logic cell
_LC116 = LCELL( _EQ014 $ GND);
_EQ014 = CP0 & DATA0
# !CP0 & _LC116
# DATA0 & _LC116;
-- Node name is '~200~1'
-- Equation name is '~200~1', location is LC121, type is buried.
-- synthesized logic cell
_LC121 = LCELL( _EQ015 $ GND);
_EQ015 = CP0 & DATA4
# !CP0 & _LC121
# DATA4 & _LC121;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\ajun\putin.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,619K
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