mult5x5.rpt

此程序能够实现4位二进制乘法

         #  _LC101 & !_LC102;

-- Node name is '|MULT4X4:2|~436~1' 
-- Equation name is '_LC101', type is buried 
-- synthesized logic cell 
_LC101   = LCELL( _EQ049 $  GND);
  _EQ049 =  _LC099 &  _LC102;

-- Node name is '|MULT4X4:2|~442~1' 
-- Equation name is '_LC075', type is buried 
-- synthesized logic cell 
_LC075   = LCELL( _EQ050 $  GND);
  _EQ050 =  _LC081 &  _LC102
         #  _LC077 & !_LC102;

-- Node name is '|MULT4X4:2|~445~1' 
-- Equation name is '_LC077', type is buried 
-- synthesized logic cell 
_LC077   = LCELL( _EQ051 $  GND);
  _EQ051 =  _LC075 &  _LC102;

-- Node name is '|MULT4X4:2|~451~1' 
-- Equation name is '_LC065', type is buried 
-- synthesized logic cell 
_LC065   = LCELL( _EQ052 $  GND);
  _EQ052 =  _LC066 &  _LC102
         #  _LC079 & !_LC102;

-- Node name is '|MULT4X4:2|~454~1' 
-- Equation name is '_LC079', type is buried 
-- synthesized logic cell 
_LC079   = LCELL( _EQ053 $  GND);
  _EQ053 =  _LC065 &  _LC102;

-- Node name is '|MULT4X4:2|~545~1' 
-- Equation name is '_LC127', type is buried 
-- synthesized logic cell 
_LC127   = LCELL( _EQ054 $  GND);
  _EQ054 =  _LC070 &  _LC098
         # !_LC070 &  _LC124;

-- Node name is '|MULT4X4:2|~551~1' 
-- Equation name is '_LC124', type is buried 
-- synthesized logic cell 
_LC124   = LCELL( _EQ055 $  GND);
  _EQ055 =  _LC070 &  _LC127;

-- Node name is '|MULT4X4:2|~557~1' 
-- Equation name is '_LC123', type is buried 
-- synthesized logic cell 
_LC123   = LCELL( _EQ056 $  GND);
  _EQ056 =  _LC070 &  _LC097
         # !_LC070 &  _LC122;

-- Node name is '|MULT4X4:2|~560~1' 
-- Equation name is '_LC122', type is buried 
-- synthesized logic cell 
_LC122   = LCELL( _EQ057 $  GND);
  _EQ057 =  _LC070 &  _LC123;

-- Node name is '|MULT4X4:2|~566~1' 
-- Equation name is '_LC074', type is buried 
-- synthesized logic cell 
_LC074   = LCELL( _EQ058 $  GND);
  _EQ058 =  _LC070 &  _LC081
         # !_LC070 &  _LC121;

-- Node name is '|MULT4X4:2|~569~1' 
-- Equation name is '_LC121', type is buried 
-- synthesized logic cell 
_LC121   = LCELL( _EQ059 $  GND);
  _EQ059 =  _LC070 &  _LC074;

-- Node name is '|MULT4X4:2|~575~1' 
-- Equation name is '_LC067', type is buried 
-- synthesized logic cell 
_LC067   = LCELL( _EQ060 $  GND);
  _EQ060 =  _LC066 &  _LC070
         # !_LC070 &  _LC113;

-- Node name is '|MULT4X4:2|~578~1' 
-- Equation name is '_LC113', type is buried 
-- synthesized logic cell 
_LC113   = LCELL( _EQ061 $  GND);
  _EQ061 =  _LC067 &  _LC070;

-- Node name is '|PUTIN:1|~119~1' 
-- Equation name is '_LC070', type is buried 
-- synthesized logic cell 
_LC070   = LCELL( _EQ062 $  GND);
  _EQ062 = !CP0 &  CP1 &  DATA3
         #  CP0 &  _LC070
         # !CP1 &  _LC070
         #  CP1 &  DATA3 &  _LC070
         # !CP0 &  DATA3 &  _LC070;

-- Node name is '|PUTIN:1|~128~1' 
-- Equation name is '_LC102', type is buried 
-- synthesized logic cell 
_LC102   = LCELL( _EQ063 $  GND);
  _EQ063 = !CP0 &  CP1 &  DATA2
         #  CP0 &  _LC102
         # !CP1 &  _LC102
         #  CP1 &  DATA2 &  _LC102
         # !CP0 &  DATA2 &  _LC102;

-- Node name is '|PUTIN:1|~137~1' 
-- Equation name is '_LC083', type is buried 
-- synthesized logic cell 
_LC083   = LCELL( _EQ064 $  GND);
  _EQ064 = !CP0 &  CP1 &  DATA1
         #  CP0 &  _LC083
         # !CP1 &  _LC083
         #  CP1 &  DATA1 &  _LC083
         # !CP0 &  DATA1 &  _LC083;

-- Node name is '|PUTIN:1|~146~1' 
-- Equation name is '_LC082', type is buried 
-- synthesized logic cell 
_LC082   = LCELL( _EQ065 $  GND);
  _EQ065 = !CP0 &  CP1 &  DATA0
         #  CP0 &  _LC082
         # !CP1 &  _LC082
         #  CP1 &  DATA0 &  _LC082
         # !CP0 &  DATA0 &  _LC082;

-- Node name is '|PUTIN:1|~155~1' 
-- Equation name is '_LC068', type is buried 
-- synthesized logic cell 
_LC068   = LCELL( _EQ066 $  GND);
  _EQ066 = !CP0 &  CP1 &  DATA4
         #  CP0 &  _LC068
         # !CP1 &  _LC068
         #  CP1 &  DATA4 &  _LC068
         # !CP0 &  DATA4 &  _LC068;

-- Node name is '|PUTIN:1|~164~1' 
-- Equation name is '_LC098', type is buried 
-- synthesized logic cell 
_LC098   = LCELL( _EQ067 $  GND);
  _EQ067 =  CP0 &  DATA3
         # !CP0 &  _LC098
         #  DATA3 &  _LC098;

-- Node name is '|PUTIN:1|~173~1' 
-- Equation name is '_LC097', type is buried 
-- synthesized logic cell 
_LC097   = LCELL( _EQ068 $  GND);
  _EQ068 =  CP0 &  DATA2
         # !CP0 &  _LC097
         #  DATA2 &  _LC097;

-- Node name is '|PUTIN:1|~182~1' 
-- Equation name is '_LC081', type is buried 
-- synthesized logic cell 
_LC081   = LCELL( _EQ069 $  GND);
  _EQ069 =  CP0 &  DATA1
         # !CP0 &  _LC081
         #  DATA1 &  _LC081;

-- Node name is '|PUTIN:1|~191~1' 
-- Equation name is '_LC066', type is buried 
-- synthesized logic cell 
_LC066   = LCELL( _EQ070 $  GND);
  _EQ070 =  CP0 &  DATA0
         # !CP0 &  _LC066
         #  DATA0 &  _LC066;

-- Node name is '|PUTIN:1|~200~1' 
-- Equation name is '_LC073', type is buried 
-- synthesized logic cell 
_LC073   = LCELL( _EQ071 $  _EQ072);
  _EQ071 =  CP0 &  DATA4 &  _X025;
  _X025  = EXP(!CP0 &  _LC073);
  _EQ072 = !CP0 &  _LC073;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        d:\ajun\mult5x5.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 7,074K