defts201.h

基于ADSP TS201的DMA传输程序

#define SQCTL_NMOD_P (9)
#define SQCTL_TRCBEN_P (10)
#define SQCTL_TRCBEXEN_P (11)

// Bit Masks
#define SQCTL_GIE MAKE_BITMASK_(SQCTL_GIE_P)
#define SQCTL_SW MAKE_BITMASK_(SQCTL_SW_P)
#define SQCTL_DBGDSBL MAKE_BITMASK_(SQCTL_DBGDSBL_P)
#define SQCTL_NMOD MAKE_BITMASK_(SQCTL_NMOD_P)
#define SQCTL_TRCBEN MAKE_BITMASK_(SQCTL_TRCBEN_P)
#define SQCTL_TRCBEXEN MAKE_BITMASK_(SQCTL_TRCBEXEN_P)

//* SQSTAT With Bit Defines *

#define SQSTAT_LOC (0x1E035B)

// Bit positions (of the masks)
#define SQSTAT_MODE_P (0)
#define SQSTAT_IDLE_P (2)
#define SQSTAT_SPVCMD_P (3)
#define SQSTAT_EXCAUSE_P (8)
#define SQSTAT_EMCAUSE_P (12)
#define SQSTAT_FLG_P (16)
#define SQSTAT_GIE_P (20)
#define SQSTAT_SW_P (21)
#define SQSTAT_EMU_P (22)
#define SQSTAT_BTBEN_P (24)
#define SQSTAT_BTBLK_P (25)

// Bit masks
#define SQSTAT_MODE (0x00000003)
#define SQSTAT_IDLE (0x00000004)
#define SQSTAT_SPVCMD (0x000000F8)
#define SQSTAT_EXCAUSE (0x00000F00)
#define SQSTAT_EMCAUSE (0x0000F000)
#define SQSTAT_FLG (0x000F0000)

//* SFREG With Bit Defines *

#define SFREG_LOC (0x1E035C)

// Bit positions
#define SFREG_GSCF0_P (0)
#define SFREG_GSCF1_P (1)
#define SFREG_XSCF0_P (2)
#define SFREG_XSCF1_P (3)
#define SFREG_YSCF0_P (4)
#define SFREG_YSCF1_P (5)

// Bit Masks
#define SFREG_GSCF0 MAKE_BITMASK_(SFREG_GSCF0_P )
#define SFREG_GSCF1 MAKE_BITMASK_(SFREG_GSCF1_P )
#define SFREG_XSCF0 MAKE_BITMASK_(SFREG_XSCF0_P )
#define SFREG_XSCF1 MAKE_BITMASK_(SFREG_XSCF1_P )
#define SFREG_YSCF0 MAKE_BITMASK_(SFREG_YSCF0_P )
#define SFREG_YSCF1 MAKE_BITMASK_(SFREG_YSCF1_P )

//* Emulation Registers I *

//* Watchpoint Registers *

#define WP0CTL_LOC (0x1E0360)
#define WP1CTL_LOC (0x1E0361)
#define WP2CTL_LOC (0x1E0362)

// Bit Masks
// OPMODE
#define WPCTL_DSBL (0x00000000)
#define WPCTL_ADDRESS (0x00000001)
#define WPCTL_RANGE (0x00000002)
#define WPCTL_NOTRANGE (0x00000003)
// EXTYPE
#define WPCTL_NOEXCEPT (0x0000000)
#define WPCTL_EXCEPT (0x00000004)
#define WPCTL_EMUTRAP (0x00000008)
// SSTP, WP0CTL
#define WPCTL_SSTP (0x00000010)
// R/W, WP1CTL and WP2CTL
#define WPCTL_READ (0x00000010)
#define WPCTL_WRITE (0x00000020)
// JK, WP1CTL
#define WPCTL_JK_JBUS (0x00000040)
#define WPCTL_JK_KBUS (0x00000080)
#define WPCTL_JK_BOTH (0x000000C0)

#define WP0STAT_LOC (0x1E0364)
#define WP1STAT_LOC (0x1E0365)
#define WP2STAT_LOC (0x1E0366)

// Bit positions (of the masks)
#define WPSTAT_VALUE_P (0)
#define WPSTAT_EX_P (16)

// Bit masks
#define WPSTAT_VALUE (0x0000FFFF)
#define WPSTAT_EX (0x00030000)

#define WP0L_LOC (0x1E0368)
#define WP0H_LOC (0x1E0369)
#define WP1L_LOC (0x1E036A)
#define WP1H_LOC (0x1E036B)
#define WP2L_LOC (0x1E036C)
#define WP2H_LOC (0x1E036D)

#define CCNT0_LOC (0x1E0370)
#define CCNT1_LOC (0x1E0371)
#define PRFM_LOC (0x1E0372)

// Bit Masks
// Non Granted Requests
#define PRFM_NGR_SEQ (0)
#define PRFM_NGR_JALU (1)
#define PRFM_NGR_KALU (2)
#define PRFM_NGR_SOC (3)

// Granted Requests
#define PRFM_GR_SEQ (4)
#define PRFM_GR_JALU (5)
#define PRFM_GR_KALU (6)
#define PRFM_GR_SOC (7)

// Module Used
#define PRFM_MODULE_JALU (8)
#define PRFM_MODULE_KALU (9)
#define PRFM_MODULE_CBX (10)
#define PRFM_MODULE_CBY (11)
#define PRFM_MODULE_CTRL (12)

#define PRFM_SCYCLE (16)
#define PRFM_BTBPR (17)
#define PRFM_ISL (18)
#define PRFM_CCYCLE (19)
#define PRFM_SUMEN (31)

#define PRFCNT_LOC (0x1E0373)

#define TRCBMASK_LOC (0x1E0374)
#define TRCBPTR_LOC (0x1E0375)

//* Cache Registers With Bit Defines *
// Command registers
#define CACMD0_LOC (0x1E03C0)
#define CACMD2_LOC (0x1E03C8)
#define CACMD4_LOC (0x1E03D0)
#define CACMD6_LOC (0x1E03D8)
#define CACMD8_LOC (0x1E03E0)
#define CACMD10_LOC (0x1E03E8)
#define CACMDB_LOC (0x1E03FC)

// Bit Masks
#define CACMD_EN (0x00000000)
#define CACMD_DIS (0x04000000)
#define CACMD_SET_BUS (0x1c000000)
#define CACMD_SLOCK (0x08000000)
#define CACMD_ELOCK (0x0c000000)
#define CACMD_CB (0x10000000)
#define CACMD_INV (0x14000000)
#define CACHE_INIT (0x40000000)
#define CACHE_INIT_LOCK (0x44000000)
#define CACMD_REFRESH (0x50000000)

#define CACMD_NOSTALL (0x00004000)

#define CACMD_K_BUS_N_ (0x000000)
#define CACMD_K_BUS_R_ (0x008000)
#define CACMD_K_BUS_W_ (0x010000)
#define CACMD_K_BUS_RW (0x018000)
#define CACMD_J_BUS_N_ (0x000000)
#define CACMD_J_BUS_R_ (0x020000)
#define CACMD_J_BUS_W_ (0x040000)
#define CACMD_J_BUS_RW (0x060000)
#define CACMD_S_BUS_N_ (0x000000)
#define CACMD_S_BUS_R_ (0x080000)
#define CACMD_S_BUS_W_ (0x100000)
#define CACMD_S_BUS_RW (0x180000)
#define CACMD_I_BUS_N_ (0x000000)
#define CACMD_I_BUS_R_ (0x200000)

// Bit Positions
#define CACMD_LEN_P (15)

// Address/Index registers
#define CCAIR0_LOC (0x1E03C1)
#define CCAIR2_LOC (0x1E03C9)
#define CCAIR4_LOC (0x1E03D1)
#define CCAIR6_LOC (0x1E03D9)
#define CCAIR8_LOC (0x1E03E1)
#define CCAIR10_LOC (0x1E03E9)
#define CCAIRB_LOC (0x1E03FD)

// Status registers
#define CASTAT0_LOC (0x1E03C2)
#define CASTAT2_LOC (0x1E03CA)
#define CASTAT4_LOC (0x1E03D2)
#define CASTAT6_LOC (0x1E03DA)
#define CASTAT8_LOC (0x1E03E2)
#define CASTAT10_LOC (0x1E03EA)

// Bit Positions
#define CASTAT_ENBL_P (14)
#define CASTAT_LOCK_P (15)
#define CASTAT_COM_ACTIVE_P (16)
#define CASTAT_COM_ABRTD_P (17)
#define CASTAT_STL_ACTIVE_P (19)
#define CASTAT_K_CACHING_P (20)
#define CASTAT_J_CACHING_P (22)
#define CASTAT_S_CACHING_P (24)
#define CASTAT_I_CACHING_P (26)

// Bit Masks
#define CASTAT_REFCNTR (0x00003fff)
#define CASTAT_ENBL MAKE_BITMASK_(CASTAT_ENBL_P)
#define CASTAT_LOCK MAKE_BITMASK_(CASTAT_LOCK_P)
#define CASTAT_COM_ACTIVE MAKE_BITMASK_(CASTAT_COM_ACTIVE_P)
#define CASTAT_COM_ABRTD MAKE_BITMASK_(CASTAT_COM_ABRTD_P)

#define CADATA0_LOC (0x1E03C3)
#define CADATA2_LOC (0x1E03CB)
#define CADATA4_LOC (0x1E03D3)
#define CADATA6_LOC (0x1E03DB)
#define CADATA8_LOC (0x1E03E3)
#define CADATA10_LOC (0x1E03EB)
#define CADATAB_LOC (0x1E03FF)

//* Cache Commands Macros *

#if !defined(SET_REFRESH0_)
#define SET_REFRESH0_(x_) () // Make a bit mask from a bit position
#endif

//* TCBs With Bit Defines *

#define DCS0_LOC (0x1F0000)
#define DCD0_LOC (0x1F0004)
#define DCS1_LOC (0x1F0008)
#define DCD1_LOC (0x1F000c)
#define DCS2_LOC (0x1F0010)
#define DCD2_LOC (0x1F0014)
#define DCS3_LOC (0x1F0018)
#define DCD3_LOC (0x1F001C)
#define DC4_LOC (0x1F0020)
#define DC5_LOC (0x1F0024)
#define DC6_LOC (0x1F0028)
#define DC7_LOC (0x1F002C)
#define DC8_LOC (0x1F0040)
#define DC9_LOC (0x1F0044)
#define DC10_LOC (0x1F0048)
#define DC11_LOC (0x1F004C)
#define DC12_LOC (0x1F0058)
#define DC13_LOC (0x1F005C)

// TYPES (TY)
#define TCB_EPROM (0xC0000000)
#define TCB_FLYBY (0xA0000000)
#define TCB_EXTMEM (0x80000000)
#define TCB_INTMEM (0x40000000)
#define TCB_LINK (0x20000000)
#define TCB_DISABLE (0x00000000)
// PRIORITY (PR)
#define TCB_HPRIORITY (0x10000000)
// 2DDMA
#define TCB_TWODIM (0x08000000)
// OPERAND LENGTH (LEN)
#define TCB_QUAD (0x06000000)
#define TCB_LONG (0x04000000)
#define TCB_NORMAL (0x02000000)
// INTERRUPT (INT)
#define TCB_INT (0x01000000)
// DMA REQUEST (DRQ)
#define TCB_DMAR (0x00800000)
// CHAINING ENABLE (CHEN)
#define TCB_CHAIN (0x00400000)
// CHAINED CHANNEL (CHTG)
#define TCB_DMA8DEST (0x00000000)
#define TCB_DMA9DEST (0x00080000)
#define TCB_DMA10DEST (0x00100000)
#define TCB_DMA11DEST (0x00180000)
#define TCB_DMA4DEST (0x00200000)
#define TCB_DMA5DEST (0x00280000)
#define TCB_DMA6DEST (0x00300000)
#define TCB_DMA7DEST (0x00380000)

//* DMA Controls With Bit Defines *
#define DCNT_LOC (0x1F0060)
#define DCNTST_LOC (0x1F0064)
#define DCNTCL_LOC (0x1F0068)

// Bit positions
#define DCNT_DMA0_P (0)
#define DCNT_DMA1_P (1)
#define DCNT_DMA2_P (2)
#define DCNT_DMA3_P (3)
#define DCNT_DMA4_P (4)
#define DCNT_DMA5_P (5)
#define DCNT_DMA6_P (6)
#define DCNT_DMA7_P (7)
#define DCNT_DMA8_P (10)
#define DCNT_DMA9_P (11)
#define DCNT_DMA10_P (12)
#define DCNT_DMA11_P (13)
#define DCNT_DMA12_P (16)
#define DCNT_DMA13_P (17)

// Bit Masks
#define DCNT_DMA0 MAKE_BITMASK_(DCNT_DMA0_P)
#define DCNT_DMA1 MAKE_BITMASK_(DCNT_DMA1_P)
#define DCNT_DMA2 MAKE_BITMASK_(DCNT_DMA2_P)
#define DCNT_DMA3 MAKE_BITMASK_(DCNT_DMA3_P)
#define DCNT_DMA4 MAKE_BITMASK_(DCNT_DMA4_P)
#define DCNT_DMA5 MAKE_BITMASK_(DCNT_DMA5_P)
#define DCNT_DMA6 MAKE_BITMASK_(DCNT_DMA6_P)
#define DCNT_DMA7 MAKE_BITMASK_(DCNT_DMA7_P)
#define DCNT_DMA8 MAKE_BITMASK_(DCNT_DMA8_P)
#define DCNT_DMA9 MAKE_BITMASK_(DCNT_DMA9_P)
#define DCNT_DMA10 MAKE_BITMASK_(DCNT_DMA10_P)
#define DCNT_DMA11 MAKE_BITMASK_(DCNT_DMA11_P)
#define DCNT_DMA12 MAKE_BITMASK_(DCNT_DMA12_P)
#define DCNT_DMA13 MAKE_BITMASK_(DCNT_DMA13_P)

//* DMA Status With Bit Defines *
#define DSTATL_LOC (0x1F006C)
#define DSTATCL_LOC (0x1F0070)

// Bit Masks
#define DSTAT_IDLE (0x00000000)
#define DSTAT_ACT (0x00000001)
#define DSTAT_DONE (0x00000002)
#define DSTAT_ACT_ERR (0x00000004)
#define DSTAT_CFG_ERR (0x00000005)
#define DSTAT_ADD_ERR (0x00000007)

// Field Extracts - use with fext instruction
#define DSTATL0 (0x0003) // 0th position of length 3
#define DSTATL1 (0x0303) // 3rd position of length 3
#define DSTATL2 (0x0603) // 6th position of length 3
#define DSTATL3 (0x0903) // 9th position of length 3
#define DSTATL4 (0x0C03) // 12th position of length 3
#define DSTATL5 (0x0F03) // 15th position of length 3
#define DSTATL6 (0x1203) // 18th position of length 3
#define DSTATL7 (0x1503) // 21st position of length 3

#define DSTATH_LOC (0x1F006D)
#define DSTATCH_LOC (0x1F0071)

#define DSTATH8 (0x0003) // 0th position of length 3
#define DSTATH9 (0x0303) // 3rd position of length 3
#define DSTATH10 (0x0603) // 6th position of length 3
#define DSTATH11 (0x0903) // 9th position of length 3
#define DSTATH12 (0x1203) // 18th position of length 3
#define DSTATH13 (0x1503) // 21st position of length 3

//* SYSCON register With Bit Masks *
#define SYSCON_LOC (0x1F0080)

// Bit Masks
#define SYSCON_MS0_IDLE (0x00000001)
#define SYSCON_MS0_WT0 (0x00000000)
#define SYSCON_MS0_WT1 (0x00000002)
#define SYSCON_MS0_WT2 (0x00000004)
#define SYSCON_MS0_WT3 (0x00000006)
#define SYSCON_MS0_PIPE1 (0x00000000)
#define SYSCON_MS0_PIPE2 (0x00000008)
#define SYSCON_MS0_PIPE3 (0x00000010)
#define SYSCON_MS0_PIPE4 (0x00000018)
#define SYSCON_MS0_SLOW (0x00000020)
#define SYSCON_MS1_IDLE (SYSCON_MS0_IDLE << 6)
#define SYSCON_MS1_WT0 (SYSCON_MS0_WT0 << 6)
#define SYSCON_MS1_WT1 (SYSCON_MS0_WT1 << 6)
#define SYSCON_MS1_WT2 (SYSCON_MS0_WT2 << 6)
#define SYSCON_MS1_WT3 (SYSCON_MS0_WT3 << 6)
#define SYSCON_MS1_PIPE1 (SYSCON_MS0_PIPE1 << 6)
#define SYSCON_MS1_PIPE2 (SYSCON_MS0_PIPE2 << 6)
#define SYSCON_MS1_PIPE3 (SYSCON_MS0_PIPE3 << 6)
#define SYSCON_MS1_PIPE4 (SYSCON_MS0_PIPE4 << 6)
#define SYSCON_MS1_SLOW (SYSCON_MS0_SLOW << 6)
#define SYSCON_MSH_IDLE (SYSCON_MS0_IDLE << 12)
#define SYSCON_MSH_WT0 (SYSCON_MS0_WT0 << 12)
#define SYSCON_MSH_WT1 (SYSCON_MS0_WT1 << 12)
#define SYSCON_MSH_WT2 (SYSCON_MS0_WT2 << 12)
#define SYSCON_MSH_WT3 (SYSCON_MS0_WT3 << 12)
#define SYSCON_MSH_PIPE1 (SYSCON_MS0_PIPE1 << 12)
#define SYSCON_MSH_PIPE2 (SYSCON_MS0_PIPE2 << 12)
#define SYSCON_MSH_PIPE3 (SYSCON_MS0_PIPE3 << 12)
#define SYSCON_MSH_PIPE4 (SYSCON_MS0_PIPE4 << 12)
#define SYSCON_MSH_SLOW (SYSCON_MS0_SLOW << 12)
#define SYSCON_MEM_WID64 (0x00080000)
#define SYSCON_MP_WID64 (0x00100000)
#define SYSCON_HOST_WID64 (0x00200000)

//* BUSLOCK register *
#define BUSLOCK_LOC (0x1F0083)

//* SDRCON register With Bit Masks *
#define SDRCON_LOC (0x1F0084)

// Bit Masks
#define SDRCON_ENBL (0x00000001)
#define SDRCON_CLAT1 (0x00000000)
#define SDRCON_CLAT2 (0x00000002)
#define SDRCON_CLAT3 (0x00000004)
#define SDRCON_PIPE1 (0x00000008)
#define SDRCON_PG256 (0x00000000)
#define SDRCON_PG512 (0x00000010)
#define SDRCON_PG1K (0x00000020)
#define SDRCON_REF1100 (0x00000000)
#define SDRCON_REF1850 (0x00000080)
#define SDRCON_REF2200 (0x00000100)
#define SDRCON_REF3700 (0x00000180)
#define SDRCON_PC2RAS2 (0x00000000)
#define SDRCON_PC2RAS3 (0x00000200)
#define SDRCON_PC2RAS4 (0x00000400)
#define SDRCON_PC2RAS5 (0x00000600)
#define SDRCON_RAS2PC2 (0x00000000)
#define SDRCON_RAS2PC3 (0x00000800)
#define SDRCON_RAS2PC4 (0x00001000)
#define SDRCON_RAS2PC5 (0x00001800)
#define SDRCON_RAS2PC6 (0x00002000)
#define SDRCON_RAS2PC7 (0x00002800)
#define SDRCON_RAS2PC8 (0x00003000)
#define SDRCON_INIT (0x00004000)
#define SDRCON_EMRS (0x00008000)

//* SYSTAT registers *
#define SYSTAT_LOC (0x1F0086)
#define SYSTATCL_LOC (0x1F0087)

//* BMAX registers *
#define BMAX_LOC (0x1F008C)
#define BMAXC_LOC (0x1F008D)

//* Link Buffer Registers *
#define LBUFTX0_LOC (0x1F00A0)
#define LBUFRX0_LOC (0x1F00A4)
#define LBUFTX1_LOC (0x1F00A8)
#define LBUFRX1_LOC (0x1F00AC)
#define LBUFTX2_LOC (0x1F00B0)
#define LBUFRX2_LOC (0x1F00B4)
#define LBUFTX3_LOC (0x1F00B8)
#define LBUFRX3_LOC (0x1F00BC)

//* Link Receive Control Registers with Bit Masks *
#define LRCTL0_LOC (0x1F00E0)
#define LRCTL1_LOC (0x1F00E1)
#define LRCTL2_LOC (0x1F00E2)
#define LRCTL3_LOC (0x1F00E3)

// Bit positions
#define LRCTL_REN_P (0)
#define LRCTL_RVERE_P (1)
#define LRCTL_RTOE_P (2)
#define LRCTL_RBCMPE_P (3)