regkeys

FPGA-Seven segment and counter

s
prop_420_name
PROP_parGenClkRegionRpt
s
prop_420_val
"false"
s
prop_421_name
PROP_parGenTimingRpt
s
prop_421_val
"true"
s
prop_422_name
PROP_parGenSimModel
s
prop_422_val
"false"
s
prop_423_name
PROP_parPowerReduction
s
prop_423_val
"false"
s
prop_424_name
PROP_mpprViewParRptForSelRslt
s
prop_424_val
""
s
prop_425_name
PROP_mpprViewPadRptForSelRslt
s
prop_425_val
""
s
prop_426_name
PROP_parMpprParIterations
s
prop_426_val
"3"
s
prop_427_name
PROP_parMpprResultsToSave
s
prop_427_val
""
s
prop_428_name
PROP_parMpprResultsDirectory
s
prop_428_val
""
s
prop_429_name
PROP_parMpprNodelistFile
s
prop_429_val
""
s
prop_42_name
PROP_XPORTOutFileType
s
prop_42_val
"VHDL"
s
prop_430_name
PROP_xilxBitgCfg_GenOpt_DbgBitStr
s
prop_430_val
"false"
s
prop_431_name
PROP_xilxBitgReadBk_GenBitStr
s
prop_431_val
"false"
s
prop_432_name
PROP_xilxBitgCfg_GenOpt_LogicAllocFile
s
prop_432_val
"false"
s
prop_433_name
PROP_xilxBitgCfg_GenOpt_MaskFile
s
prop_433_val
"false"
s
prop_434_name
PROP_AceActiveName
s
prop_434_val
""
s
prop_435_name
PROP_impactConfigFileName
s
prop_435_val
""
s
prop_436_name
PROP_SynthRAMStyle
s
prop_436_val
"Auto"
s
prop_437_name
PROP_xstROMStyle
s
prop_437_val
"Auto"
s
prop_438_name
PROP_SynthMuxStyle
s
prop_438_val
"Auto"
s
prop_439_name
PROP_xstMoveFirstFfStage
s
prop_439_val
"true"
s
prop_43_name
PROP_XPORTlistInpFiles
s
prop_43_val
"false"
s
prop_440_name
PROP_xstMoveLastFfStage
s
prop_440_val
"true"
s
prop_441_name
PROP_MapPowerReduction
s
prop_441_val
"false"
s
prop_442_name
PROPEXT_SynthFrequencySyn_virtex
s
prop_442_val
"0.0"
s
prop_443_name
PROP_MapEffortLevel
s
prop_443_val
"Medium"
s
prop_444_name
PROP_bitgen_Encrypt_Encrypt
s
prop_444_val
"false"
s
prop_445_name
PROP_MapPlacerCostTable
s
prop_445_val
"1"
s
prop_446_name
PROP_MapLogicOptimization
s
prop_446_val
"false"
s
prop_447_name
PROP_MapRegDuplication
s
prop_447_val
"false"
s
prop_448_name
PROP_MapSmartGuideFileName
s
prop_448_val
"TopDesign_guide.ncd"
s
prop_449_name
PROP_ParSmartGuideFileName
s
prop_449_val
"TopDesign_guide.ncd"
s
prop_44_name
PROP_SimModelGenerateTestbenchFile
s
prop_44_val
"false"
s
prop_450_name
PROP_DevFamilyPMName
s
prop_450_val
"spartan3e"
s
prop_451_name
PROP_DevDevice
s
prop_451_val
"xc3s1200e"
s
prop_452_name
PROP_CompxlibSimPath
s
prop_452_val
"C:/Program Files/Modeltech_6.4a/win32"
s
prop_453_name
PROP_CompxlibLang
s
prop_453_val
"All"
s
prop_454_name
PROP_SimModelGenMultiHierFile
s
prop_454_val
"false"
s
prop_455_name
PROP_ISimSimulationRunTime_par_tb
s
prop_455_val
"1000 ns"
s
prop_456_name
PROP_ISimSimulationRunTime_par_tbw
s
prop_456_val
"1000 ns"
s
prop_457_name
PROP_ISimSimulationRunTime_behav_tb
s
prop_457_val
"1000 ns"
s
prop_458_name
PROP_ISimSimulationRunTime_behav_tbw
s
prop_458_val
"1000 ns"
s
prop_459_name
PROP_ISimVCDFileName_par_tb
s
prop_459_val
"xpower.vcd"
s
prop_45_name
PROP_SimModelInsertBuffersPulseSwallow
s
prop_45_val
"false"
s
prop_460_name
PROP_ISimVCDFileName_par_tbw
s
prop_460_val
"xpower.vcd"
s
prop_461_name
PROP_xilxPARextraEffortLevel
s
prop_461_val
"None"
s
prop_462_name
PROP_parPowerActivityFile
s
prop_462_val
""
s
prop_463_name
PROP_CompxlibSmartModels
s
prop_463_val
"true"
s
prop_464_name
PROP_CompxlibUpdateIniForSmartModel
s
prop_464_val
"false"
s
prop_465_name
PROP_MapPowerActivityFile
s
prop_465_val
""
s
prop_466_name
PROP_bitgen_Encrypt_keyFile
s
prop_466_val
""
s
prop_467_name
PROP_bitgen_Encrypt_key0
s
prop_467_val
""
s
prop_468_name
PROP_bitgen_Encrypt_key1
s
prop_468_val
""
s
prop_469_name
PROP_bitgen_Encrypt_key2
s
prop_469_val
""
s
prop_46_name
PROP_SimModelOtherNetgenOpts
s
prop_46_val
""
s
prop_470_name
PROP_bitgen_Encrypt_key3
s
prop_470_val
""
s
prop_471_name
PROP_bitgen_Encrypt_key4
s
prop_471_val
""
s
prop_472_name
PROP_bitgen_Encrypt_key5
s
prop_472_val
""
s
prop_473_name
PROP_MapExtraEffort
s
prop_473_val
"None"
s
prop_474_name
PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2
s
prop_474_val
"false"
s
prop_475_name
PROP_DevPackage
s
prop_475_val
"fg320"
s
prop_476_name
PROP_Synthesis_Tool
s
prop_476_val
"XST (VHDL/Verilog)"
s
prop_477_name
PROP_CompxlibUniSimLib
s
prop_477_val
"true"
s
prop_478_name
PROP_CompxlibUni9000Lib
s
prop_478_val
"true"
s
prop_479_name
PROP_xilxBitgReadBk_GenBitStr_virtex2
s
prop_479_val
"false"
s
prop_47_name
PROP_SimModelRetainHierarchy
s
prop_47_val
"true"
s
prop_480_name
PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex2
s
prop_480_val
"false"
s
prop_481_name
PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2
s
prop_481_val
"false"
s
prop_482_name
PROP_DevSpeed
s
prop_482_val
"-5"
s
prop_483_name
PROP_PreferredLanguage
s
prop_483_val
"VHDL"
s
prop_484_name
PROP_HdlTemplateLang
s
prop_484_val
"VHDL"
s
prop_485_name
PROP_schFuncModelTargetLang
s
prop_485_val
"VHDL"
s
prop_486_name
PROP_schInstTempTargetLang
s
prop_486_val
"VHDL"
s
prop_487_name
PROP_hdlInstTempTargetLang
s
prop_487_val
"VHDL"
s
prop_488_name
PROP_ChangeDevSpeed
s
prop_488_val
"-5"
s
prop_489_name
PROP_SimModelTarget
s
prop_489_val
"VHDL"
s
prop_48_name
PROP_CorgenRegenCore
s
prop_48_val
"Under Current Project Setting"
s
prop_490_name
PROP_xawHdlSourceTargetLang
s
prop_490_val
"VHDL"
s
prop_491_name
PROP_tbwTestbenchTargetLang
s
prop_491_val
"VHDL"
s
prop_492_name
PROP_coregenFuncModelTargetLang
s
prop_492_val
"VHDL"
s
prop_493_name
PROP_xmpInstTempTargetLang
s
prop_493_val
"VHDL"
s
prop_494_name
PROP_sysgenInstTempTargetLang
s
prop_494_val
"VHDL"
s
prop_495_name
PROP_xilxPreTrceSpeed
s
prop_495_val
"-5"
s
prop_496_name
PROP_xilxPostTrceSpeed
s
prop_496_val
"-5"
s
prop_497_name
PROP_HdlTemplateName
s
prop_497_val
"TopDesign.vhd"
s
prop_498_name
PROP_SimModelRenTopLevArchTo
s
prop_498_val
"Structure"
s
prop_499_name
PROP_SimModelGenArchOnly
s
prop_499_val
"false"
s
prop_49_name
PROP_SynthOpt
s
prop_49_val
"Speed"
s
prop_4_name
PROP_HierarchicalProjectType
s
prop_4_val
"N/A"
s
prop_500_name
PROP_SimModelOutputExtIdent
s
prop_500_val
"false"
s
prop_501_name
PROP_SimModelRenTopLevMod
s
prop_501_val
""
s
prop_502_name
PROP_SimModelIncUselibDirInVerilogFile
s
prop_502_val
"false"
s
prop_503_name
PROP_SimModelIncSdfAnnInVerilogFile
s
prop_503_val
"true"
s
prop_504_name
PROP_SimModelNoEscapeSignal
s
prop_504_val
"false"
s
prop_505_name
PROP_netgenPostXlateSimModelName
s
prop_505_val
"TopDesign_translate.vhd"
s
prop_506_name
PROP_netgenPostMapSimModelName
s
prop_506_val
"TopDesign_map.vhd"
s
prop_507_name
PROP_netgenPostParSimModelName
s
prop_507_val
"TopDesign_timesim.vhd"
s
prop_508_name
PROP_bencherPostXlateTestbenchName
s
prop_508_val
""
s
prop_509_name
PROP_bencherPostMapTestbenchName
s
prop_509_val
""
s
prop_50_name
PROP_SynthOptEffort
s
prop_50_val
"Normal"
s
prop_510_name
PROP_bencherPostParTestbenchName
s
prop_510_val
""
s
prop_511_name
PROP_SimModelIncSimprimInVerilogFile
s
prop_511_val
"false"
s
prop_512_name
PROP_SimModelIncUnisimInVerilogFile
s
prop_512_val
"false"
s
prop_513_name
PROP_netgenPostSynthesisSimModelName
s
prop_513_val
"TopDesign_synthesis.vhd"
s
prop_514_name
PROP_SimModelAutoInsertGlblModuleInNetlist
s
prop_514_val
"true"
s
prop_515_name
PROP_PostXlateSimModelName
s
prop_515_val
"TopDesign_translate.vhd"
s
prop_516_name
PROP_PostMapSimModelName
s
prop_516_val
"TopDesign_map.vhd"
s
prop_517_name
PROP_PostParSimModelName
s
prop_517_val
"TopDesign_timesim.vhd"
s
prop_518_name
PROP_PostParSimModelName
s
prop_518_val
"TopDesign_timesim.vhd"
s
prop_519_name
PROP_PostParSimModelName
s
prop_519_val
"TopDesign_timesim.vhd"
s
prop_51_name
PROP_xstUseSynthConstFile
s
prop_51_val
"true"
s
prop_520_name
PROP_tbwPostXlateTestbenchName
s
prop_520_val
""
s
prop_521_name
PROP_tbwPostXlateTestbenchName
s
prop_521_val
""
s
prop_522_name
PROP_tbwPostMapTestbenchName
s
prop_522_val
""
s
prop_523_name
PROP_tbwPostMapTestbenchName
s
prop_523_val
""
s
prop_524_name
PROP_tbwPostParTestbenchName
s
prop_524_val
""
s
prop_525_name
PROP_tbwPostParTestbenchName
s
prop_525_val
""
s
prop_526_name
PROP_tbwPostParTestbenchName
s
prop_526_val
""
s
prop_527_name
PROP_tbwPostParTestbenchName
s
prop_527_val
""
s
prop_528_name
PROP_PostSynthesisSimModelName
s
prop_528_val
"TopDesign_synthesis.vhd"
s
prop_529_name
PROP_SimModelBringOutGtsNetAsAPort
s
prop_529_val
"false"
s
prop_52_name
PROP_xstLibSearchOrder
s
prop_52_val
""
s
prop_530_name
PROP_SimModelBringOutGsrNetAsAPort
s
prop_530_val
"false"
s
prop_531_name
PROP_netgenRenameTopLevEntTo
s
prop_531_val
"TopDesign"
s
prop_532_name
PROP_SimModelPathUsedInSdfAnn
s
prop_532_val
"Default"
s
prop_53_name
PROP_xstCase
s
prop_53_val
"Maintain"
s
prop_54_name
PROP_xstWorkDir
s
prop_54_val
"./xst"
s
prop_55_name
PROP_xstIniFile
s
prop_55_val
""
s
prop_56_name
PROP_xstVerilog2001
s
prop_56_val
"true"
s
prop_57_name
PROP_xstVeriIncludeDir_Global
s
prop_57_val
""
s
prop_58_name
PROP_xstUserCompileList
s
prop_58_val
""
s
prop_59_name
PROP_xstGenericsParameters
s
prop_59_val
""
s
prop_5_name
PROP_ProjectGeneratorType
s
prop_5_val
"ProjNav"
s
prop_60_name
PROP_xstVerilogMacros
s
prop_60_val
""
s
prop_61_name
PROP_xst_otherCmdLineOptions
s
prop_61_val
""
s
prop_62_name
PROP_xstGenerateRTLNetlist
s
prop_62_val
"Yes"
s
prop_63_name
PROP_xstHierarchySeparator
s
prop_63_val
"/"
s
prop_64_name
PROP_xstBusDelimiter
s
prop_64_val
"<>"
s
prop_65_name
PROP_SynthFsmEncode
s
prop_65_val
"Auto"
s
prop_66_name
PROP_SynthCaseImplStyle
s
prop_66_val
"None"
s
prop_67_name
PROP_SynthResSharing
s
prop_67_val
"true"
s
prop_68_name
PROP_SynthExtractMux
s
prop_68_val
"Yes"
s
prop_69_name
PROP_xilxSynthAddIObuf
s
prop_69_val
"true"
s
prop_6_name
PROP_Parse_Target
s
prop_6_val
"synthesis"
s
prop_70_name
PROP_xstEquivRegRemoval
s
prop_70_val
"true"
s
prop_71_name
PROP_ISimUutInstName
s
prop_71_val
"UUT"
s
prop_72_name
PROP_ISimUseCustomSimCmdFile_par_tb
s
prop_72_val
"false"
s
prop_73_name
PROP_ISimUseCustomSimCmdFile_par_tbw
s
prop_73_val
"false"
s
prop_74_name
PROP_ISimUseCustomSimCmdFile_behav_tb
s
prop_74_val
"false"
s
prop_75_name
PROP_ISimUseCustomSimCmdFile_behav_tbw
s
prop_75_val
"false"
s
prop_76_name
PROP_ISimUseCustomSimCmdFile_gen_tbw
s
prop_76_val
"false"
s
prop_77_name
PROP_ISimUseCustomSimCmdFile_launch
s
prop_77_val
"false"
s
prop_78_name
PROP_isimIncreCompilation
s
prop_78_val
"true"
s
prop_79_name
PROP_isimCompileForHdlDebug
s
prop_79_val
"true"
s
prop_7_name
PROP_Top_Level_Module_Type
s
prop_7_val
"HDL"
s
prop_80_name
PROP_ISimSDFTimingToBeRead
s
prop_80_val
"Setup Time"
s
prop_81_name
PROP_isimValueRangeCheck
s
prop_81_val
"false"
s
prop_82_name
PROP_isimSpecifySearchDirectory
s
prop_82_val
""
s
prop_83_name
PROP_ISimSpecifySearchDirectoryChkSyntax
s
prop_83_val
""
s
prop_84_name
PROP_isimSpecifyDefMacroAndValue
s
prop_84_val
""
s
prop_85_name
PROP_ISimSpecifyDefMacroAndValueChkSyntax
s
prop_85_val
""
s
prop_86_name
PROP_ISimLibSearchOrderFile
s
prop_86_val
""
s
prop_87_name
PROP_ISimUseCustomCompilationOrder
s
prop_87_val
"false"
s
prop_88_name
PROP_ISimOtherCompilerOptions_behav
s
prop_88_val
""
s
prop_89_name
PROP_ISimOtherCompilerOptions_par
s
prop_89_val
""
s
prop_8_name
PROP_SynthTop
s
prop_8_val
"Architecture|TopDesign|Behavioral"
s
prop_90_name
PROP_ISimOtherCompilerOptions_fit
s
prop_90_val
""
s
prop_91_name
PROP_DefaultTBName
s
prop_91_val
"Default"
s
prop_92_name
PROP_ibiswriterShowAllModels
s
prop_92_val
"false"
s
prop_93_name
PROP_ImpactProjectFile
s
prop_93_val
"Default"
s
prop_94_name
PROP_ngdbuild_otherCmdLineOptions
s
prop_94_val
""
s
prop_95_name
PROP_SynthXORCollapse
s
prop_95_val
"true"
s
prop_96_name
PROP_xilxNgdbld_AUL
s
prop_96_val
"false"
s
prop_97_name
PROP_xilxNgdbldMacro
s
prop_97_val
""
s
prop_98_name
PROP_xilxSynthKeepHierarchy
s
prop_98_val
"No"
s
prop_99_name
PROP_xstNetlistHierarchy
s
prop_99_val
"As Optimized"
s
prop_9_name
PROP_BehavioralSimTop
s
prop_9_val
"Architecture|TopDesign|Behavioral"
s