regkeys

FPGA-Seven segment and counter

PROP_xilxBitgCfg_GenOpt_ReadBack
s
prop_260_val
"false"
s
prop_261_name
PROP_CurrentFloorplanFile
s
prop_261_val
""
s
prop_262_name
PROP_xilxPreTrceRpt
s
prop_262_val
"Verbose Report"
s
prop_263_name
PROP_xilxPreTrceRptLimit
s
prop_263_val
"3"
s
prop_264_name
PROP_xilxPreTrceAdvAna
s
prop_264_val
"false"
s
prop_265_name
PROP_xilxPreTrceUncovPath
s
prop_265_val
""
s
prop_266_name
PROP_xilxPreTrceEndpointPath
s
prop_266_val
""
s
prop_267_name
PROP_PreTrceFastPath
s
prop_267_val
"false"
s
prop_268_name
PROP_xilxPostTrceRpt
s
prop_268_val
"Verbose Report"
s
prop_269_name
PROP_xilxPostTrceRptLimit
s
prop_269_val
"3"
s
prop_26_name
PROP_SimUseCustom_launchMSim
s
prop_26_val
"false"
s
prop_270_name
PROP_xilxPostTrceAdvAna
s
prop_270_val
"false"
s
prop_271_name
PROP_xilxPostTrceUncovPath
s
prop_271_val
""
s
prop_272_name
PROP_xilxPostTrceEndpointPath
s
prop_272_val
""
s
prop_273_name
PROP_PostTrceFastPath
s
prop_273_val
"false"
s
prop_274_name
PROP_xilxPostTrceStamp
s
prop_274_val
""
s
prop_275_name
PROP_PreTrceGenTimegroups
s
prop_275_val
"false"
s
prop_276_name
PROP_PreTrceGenDatasheet
s
prop_276_val
"true"
s
prop_277_name
PROP_PostTrceGenTimegroups
s
prop_277_val
"false"
s
prop_278_name
PROP_PostTrceGenDatasheet
s
prop_278_val
"true"
s
prop_279_name
PROP_xilxPostTrceTSIFile
s
prop_279_val
""
s
prop_27_name
PROP_SimUserCompileList_launchMSim
s
prop_27_val
""
s
prop_280_name
PROP_PreTrceTSIFile
s
prop_280_val
""
s
prop_281_name
PROP_LoadPostTrceTSIFile
s
prop_281_val
"false"
s
prop_282_name
PROP_primetimeBlockRamData
s
prop_282_val
""
s
prop_283_name
PROP_primeFlatternOutputNetlist
s
prop_283_val
"false"
s
prop_284_name
PROP_primeCorrelateOutput
s
prop_284_val
"false"
s
prop_285_name
PROP_primeTopLevelModule
s
prop_285_val
""
s
prop_286_name
PROP_AutoGenFile
s
prop_286_val
"false"
s
prop_287_name
PROP_CompxlibXlnxCoreLib
s
prop_287_val
"true"
s
prop_288_name
PROP_xilxSynthGlobOpt
s
prop_288_val
"AllClockNets"
s
prop_289_name
PROP_xstAutoBRAMPacking
s
prop_289_val
"false"
s
prop_28_name
PROP_SimUseCustom_behav
s
prop_28_val
"false"
s
prop_290_name
PROP_xstBRAMUtilRatio
s
prop_290_val
"100"
s
prop_291_name
PROP_xstAsynToSync
s
prop_291_val
"false"
s
prop_292_name
PROP_xstReadCores
s
prop_292_val
"true"
s
prop_293_name
PROP_xstCoresSearchDir
s
prop_293_val
""
s
prop_294_name
PROP_xstWriteTimingConstraints
s
prop_294_val
"false"
s
prop_295_name
PROP_xstSliceUtilRatio
s
prop_295_val
"100"
s
prop_296_name
PROP_xstCrossClockAnalysis
s
prop_296_val
"false"
s
prop_297_name
PROP_xstFsmStyle
s
prop_297_val
"LUT"
s
prop_298_name
PROP_SynthExtractRAM
s
prop_298_val
"true"
s
prop_299_name
PROP_SynthExtractROM
s
prop_299_val
"true"
s
prop_29_name
PROP_SimDo
s
prop_29_val
"true"
s
prop_2_name
PROP_StartImpView
s
prop_2_val
""
s
prop_300_name
PROP_SynthDecoderExtract
s
prop_300_val
"true"
s
prop_301_name
PROP_SynthEncoderExtract
s
prop_301_val
"Yes"
s
prop_302_name
PROP_SynthShiftRegExtract
s
prop_302_val
"true"
s
prop_303_name
PROP_SynthLogicalShifterExtract
s
prop_303_val
"true"
s
prop_304_name
PROP_xilxSynthRegBalancing
s
prop_304_val
"No"
s
prop_305_name
PROP_xstPackIORegister
s
prop_305_val
"Auto"
s
prop_306_name
PROP_xstSlicePacking
s
prop_306_val
"true"
s
prop_307_name
PROP_xstTristate2Logic
s
prop_307_val
"Yes"
s
prop_308_name
PROP_xstOptimizeInsPrimtives
s
prop_308_val
"false"
s
prop_309_name
PROP_xilxSynthRegDuplication
s
prop_309_val
"true"
s
prop_30_name
PROP_SimUseCustom_postXlate
s
prop_30_val
"false"
s
prop_310_name
PROP_xstUseClockEnable
s
prop_310_val
"Yes"
s
prop_311_name
PROP_xstUseSyncSet
s
prop_311_val
"Yes"
s
prop_312_name
PROP_xstUseSyncReset
s
prop_312_val
"Yes"
s
prop_313_name
PROP_VirtexSynthAutoConstrain
s
prop_313_val
"true"
s
prop_314_name
PROP_ibiswriterGeneratePackageParasitics
s
prop_314_val
"false"
s
prop_315_name
PROP_xilxMapTimingDrivenPacking
s
prop_315_val
"false"
s
prop_316_name
PROP_xilxBitgCfg_GenOpt_IEEE1532File
s
prop_316_val
"false"
s
prop_317_name
PROP_xilxBitgCfg_GenOpt_EnableCRC
s
prop_317_val
"true"
s
prop_318_name
PROP_xilxBitgCfg_PwrDown
s
prop_318_val
"Pull Up"
s
prop_319_name
PROP_xilxBitgCfg_DCMShutdown
s
prop_319_val
"false"
s
prop_31_name
PROP_SimUseCustom_postMap
s
prop_31_val
"false"
s
prop_320_name
PROP_xilxBitgCfg_DCMBandgap
s
prop_320_val
"false"
s
prop_321_name
PROP_xilxBitgStart_Clk_MatchCycle
s
prop_321_val
"Auto"
s
prop_322_name
PROP_bitgen_Encrypt_keySeq0
s
prop_322_val
"None"
s
prop_323_name
PROP_bitgen_Encrypt_keySeq1
s
prop_323_val
"None"
s
prop_324_name
PROP_bitgen_Encrypt_keySeq2
s
prop_324_val
"None"
s
prop_325_name
PROP_bitgen_Encrypt_keySeq3
s
prop_325_val
"None"
s
prop_326_name
PROP_bitgen_Encrypt_keySeq4
s
prop_326_val
"None"
s
prop_327_name
PROP_bitgen_Encrypt_keySeq5
s
prop_327_val
"None"
s
prop_328_name
PROP_bitgen_Encrypt_startKey
s
prop_328_val
"None"
s
prop_329_name
PROP_bitgen_Encrypt_startCBC
s
prop_329_val
""
s
prop_32_name
PROP_SimUseCustom_postPar
s
prop_32_val
"false"
s
prop_330_name
PROPEXT_xilxMapGenInputK_virtex2
s
prop_330_val
"4"
s
prop_331_name
PROPEXT_SynthMultStyle_virtex2
s
prop_331_val
"Auto"
s
prop_332_name
PROPEXT_xilxSynthMaxFanout_virtex2
s
prop_332_val
"500"
s
prop_333_name
PROP_usedsp48
s
prop_333_val
"Auto"
s
prop_334_name
PROP_xstDSPUtilRatio
s
prop_334_val
"100"
s
prop_335_name
PROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3
s
prop_335_val
"As Required"
s
prop_336_name
PROPEXT_xilxSynthAddBufg_spartan3e
s
prop_336_val
"24"
s
prop_337_name
PROPEXT_xilxBitgCfg_Rate_spartan3e
s
prop_337_val
"Default (1)"
s
prop_338_name
PROP_TopDesignUnit
s
prop_338_val
""
s
prop_339_name
PROP_TopDesignUnit
s
prop_339_val
""
s
prop_33_name
PROP_ModelSimUseConfigName
s
prop_33_val
"false"
s
prop_340_name
PROP_TopDesignUnit
s
prop_340_val
""
s
prop_341_name
PROP_TopDesignUnit
s
prop_341_val
""
s
prop_342_name
PROP_TopDesignUnit
s
prop_342_val
""
s
prop_343_name
PROP_TopDesignUnit
s
prop_343_val
""
s
prop_344_name
PROP_TopDesignUnit
s
prop_344_val
""
s
prop_345_name
PROP_TopDesignUnit
s
prop_345_val
""
s
prop_346_name
PROP_TopDesignUnit
s
prop_346_val
""
s
prop_347_name
PROP_TopDesignUnit
s
prop_347_val
""
s
prop_348_name
PROP_TopDesignUnit
s
prop_348_val
""
s
prop_349_name
PROP_TopDesignUnit
s
prop_349_val
""
s
prop_34_name
PROP_MSimSDFTimingToBeRead
s
prop_34_val
"Setup Time"
s
prop_350_name
PROP_xstVeriIncludeDir
s
prop_350_val
""
s
prop_351_name
PROP_xstVeriIncludeDir
s
prop_351_val
""
s
prop_352_name
PROP_SimUserCompileList_behav
s
prop_352_val
""
s
prop_353_name
PROP_DevFamily
s
prop_353_val
"Spartan3E"
s
prop_354_name
PROP_Simulator
s
prop_354_val
"Modelsim-SE Mixed"
s
prop_355_name
PROP_SmartGuideFileName
s
prop_355_val
"TopDesign_guide.ncd"
s
prop_356_name
PROP_vsim_otherCmdLineOptions
s
prop_356_val
""
s
prop_357_name
PROP_vlog_otherCmdLineOptions
s
prop_357_val
""
s
prop_358_name
PROP_vcom_otherCmdLineOptions
s
prop_358_val
""
s
prop_359_name
PROP_ModelSimSignalWin
s
prop_359_val
"true"
s
prop_35_name
PROP_OverwriteSym
s
prop_35_val
"false"
s
prop_360_name
PROP_ModelSimWaveWin
s
prop_360_val
"true"
s
prop_361_name
PROP_ModelSimStructWin
s
prop_361_val
"true"
s
prop_362_name
PROP_ModelSimSourceWin
s
prop_362_val
"false"
s
prop_363_name
PROP_ModelSimListWin
s
prop_363_val
"false"
s
prop_364_name
PROP_ModelSimVarsWin
s
prop_364_val
"false"
s
prop_365_name
PROP_ModelSimProcWin
s
prop_365_val
"false"
s
prop_366_name
PROP_ModelSimDataWin
s
prop_366_val
"false"
s
prop_367_name
PROP_ModelSimSimRes
s
prop_367_val
"Default (1 ps)"
s
prop_368_name
PROP_SimSyntax
s
prop_368_val
"93"
s
prop_369_name
PROP_SimUseExpDeclOnly
s
prop_369_val
"true"
s
prop_36_name
PROP_CompxlibOutputDir
s
prop_36_val
"$XILINX/<language>/<simulator>"
s
prop_370_name
PROP_ModelSimSimRunTime_tb
s
prop_370_val
"1000ns"
s
prop_371_name
PROP_ModelSimUutInstName_postMap
s
prop_371_val
"UUT"
s
prop_372_name
PROP_ModelSimUutInstName_postPar
s
prop_372_val
"UUT"
s
prop_373_name
PROP_ModelSimUutInstName_postFit
s
prop_373_val
"UUT"
s
prop_374_name
PROP_SimGenVcdFile
s
prop_374_val
"false"
s
prop_375_name
PROP_SimCustom_launchMSim
s
prop_375_val
""
s
prop_376_name
PROP_SimCustom_behav
s
prop_376_val
""
s
prop_377_name
PROP_SimCustom_postXlate
s
prop_377_val
""
s
prop_378_name
PROP_SimCustom_postMap
s
prop_378_val
""
s
prop_379_name
PROP_SimCustom_postPar
s
prop_379_val
""
s
prop_37_name
PROP_CompxlibOverwriteLib
s
prop_37_val
"Overwrite"
s
prop_380_name
PROP_ModelSimSimRunTime_tbw
s
prop_380_val
"1000ns"
s
prop_381_name
PROP_ModelSimConfigName
s
prop_381_val
"Default"
s
prop_382_name
PROP_SimModelRenTopLevInstTo
s
prop_382_val
"UUT"
s
prop_383_name
PROP_SynthConstraintsFile
s
prop_383_val
""
s
prop_384_name
PROP_ISimCustomSimCmdFileName_par_tb
s
prop_384_val
""
s
prop_385_name
PROP_ISimCustomSimCmdFileName_par_tbw
s
prop_385_val
""
s
prop_386_name
PROP_ISimCustomSimCmdFileName_behav_tb
s
prop_386_val
""
s
prop_387_name
PROP_ISimCustomSimCmdFileName_behav_tbw
s
prop_387_val
""
s
prop_388_name
PROP_ISimCustomSimCmdFileName_gen_tbw
s
prop_388_val
""
s
prop_389_name
PROP_ISimCustomSimCmdFileName_launch
s
prop_389_val
""
s
prop_38_name
PROP_CompxlibOtherCompxlibOpts
s
prop_38_val
""
s
prop_390_name
PROP_ISimSimulationRun_par_tb
s
prop_390_val
"true"
s
prop_391_name
PROP_ISimSimulationRun_par_tbw
s
prop_391_val
"true"
s
prop_392_name
PROP_ISimSimulationRun_behav_tb
s
prop_392_val
"true"
s
prop_393_name
PROP_ISimSimulationRun_behav_tbw
s
prop_393_val
"true"
s
prop_394_name
PROP_ISimGenVCDFile_par_tb
s
prop_394_val
"false"
s
prop_395_name
PROP_ISimGenVCDFile_par_tbw
s
prop_395_val
"false"
s
prop_396_name
PROP_ISimCustomCompilationOrderFile
s
prop_396_val
""
s
prop_397_name
PROP_impactBaud
s
prop_397_val
"None"
s
prop_398_name
PROP_impactConfigMode
s
prop_398_val
"None"
s
prop_399_name
PROP_impactPort
s
prop_399_val
"Auto - default"
s
prop_39_name
PROP_CompxlibSimPrimatives
s
prop_39_val
"true"
s
prop_3_name
PROP_StopImpView
s
prop_3_val
"AbstractSynthesis"
s
prop_400_name
PROP_XPowerOptAdvancedVerboseRpt
s
prop_400_val
"false"
s
prop_401_name
PROP_XPowerOptMaxNumberLines
s
prop_401_val
"1000"
s
prop_402_name
PROP_xstSafeImplement
s
prop_402_val
"No"
s
prop_403_name
PROP_XplorerRunType
s
prop_403_val
"Yes"
s
prop_404_name
PROP_XplorerNumIterations
s
prop_404_val
"7"
s
prop_405_name
PROP_XplorerEnableRetiming
s
prop_405_val
"true"
s
prop_406_name
PROP_XplorerWarnToBackup
s
prop_406_val
"true"
s
prop_407_name
PROP_XplorerOtherCmdLineOptions
s
prop_407_val
""
s
prop_408_name
PROP_PrecNumOfSumPaths
s
prop_408_val
"10"
s
prop_409_name
PROP_PrecNumOfCriticalPaths
s
prop_409_val
"1"
s
prop_40_name
PROP_XPORTInpFileName
s
prop_40_val
""
s
prop_410_name
PROP_FitterOptimization_xpla3
s
prop_410_val
"Density"
s
prop_411_name
PROP_xcpldFitDesPtermLmt_xbr
s
prop_411_val
"28"
s
prop_412_name
PROP_xcpldFitDesInReg_xbr
s
prop_412_val
"true"
s
prop_413_name
PROP_mapTimingMode
s
prop_413_val
"Non Timing Driven"
s
prop_414_name
PROP_xilxMapPackfactor
s
prop_414_val
"100"
s
prop_415_name
PROP_MapRetiming
s
prop_415_val
"false"
s
prop_416_name
PROP_MapEquivalentRegisterRemoval
s
prop_416_val
"true"
s
prop_417_name
PROP_xilxPAReffortLevel
s
prop_417_val
"Standard"
s
prop_418_name
PROP_parTimingMode
s
prop_418_val
"Performance Evaluation"
s
prop_419_name
PROP_parGenAsyDlyRpt
s
prop_419_val
"false"
s
prop_41_name
PROP_XPORTInpFileType
s
prop_41_val
"ABEL"