cos2.v

来自「verilog编写的16qam调制程序」· Verilog 代码 · 共 31 行

module cos2(clk, nrst, doutcos);
    input	clk,		// clock input
		    nrst;		// active-low reset
    output[7:0]	doutcos;		// 8-bit output

    reg[3:0]	addr;		// ROM address
 
    wire[7:0]	d;		// read data from ROM

    romcos2	rom(.addr(addr), .data(d));

    always @(posedge clk or negedge nrst) begin
	if(!nrst) begin
	  
	   
	    addr <= 0;
	end
	else if(addr==9)begin
	     addr<=0;
         
         end 
    else
         addr<=addr+1;
    end

  assign doutcos=d;

 

endmodule