📄 prev_cmp_multbcd.qmsg
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "8 " "Warning: Found 8 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R\[0\] 0 " "Info: Pin \"R\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R\[1\] 0 " "Info: Pin \"R\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R\[2\] 0 " "Info: Pin \"R\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R\[3\] 0 " "Info: Pin \"R\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R\[4\] 0 " "Info: Pin \"R\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R\[5\] 0 " "Info: Pin \"R\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R\[6\] 0 " "Info: Pin \"R\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "R\[7\] 0 " "Info: Pin \"R\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "227 " "Info: Peak virtual memory: 227 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 30 14:11:13 2009 " "Info: Processing ended: Thu Apr 30 14:11:13 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:45 " "Info: Elapsed time: 00:00:45" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Info: Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 30 14:11:42 2009 " "Info: Processing started: Thu Apr 30 14:11:42 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off MultBCD -c MultBCD " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off MultBCD -c MultBCD" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "207 " "Info: Peak virtual memory: 207 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 30 14:11:56 2009 " "Info: Processing ended: Thu Apr 30 14:11:56 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Info: Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Web Edition " "Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 30 14:12:13 2009 " "Info: Processing started: Thu Apr 30 14:12:13 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off MultBCD -c MultBCD --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MultBCD -c MultBCD --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "B\[1\] R\[6\] 14.623 ns Longest " "Info: Longest tpd from source pin \"B\[1\]\" to destination pin \"R\[6\]\" is 14.623 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns B\[1\] 1 PIN PIN_AE11 7 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_AE11; Fanout = 7; PIN Node = 'B\[1\]'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { B[1] } "NODE_NAME" } } { "MultBCD.vhd" "" { Text "C:/altera/81/quartus/Xiuh/MultBCD/MultBCD.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.121 ns) + CELL(0.150 ns) 7.121 ns fulladder:I1\|Cout~9 2 COMB LCCOMB_X28_Y33_N0 2 " "Info: 2: + IC(6.121 ns) + CELL(0.150 ns) = 7.121 ns; Loc. = LCCOMB_X28_Y33_N0; Fanout = 2; COMB Node = 'fulladder:I1\|Cout~9'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.271 ns" { B[1] fulladder:I1|Cout~9 } "NODE_NAME" } } { "../Fulladder/Fulladder.vhd" "" { Text "C:/altera/81/quartus/Xiuh/Fulladder/Fulladder.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.248 ns) + CELL(0.150 ns) 7.519 ns fulladder:I2\|S 3 COMB LCCOMB_X28_Y33_N26 2 " "Info: 3: + IC(0.248 ns) + CELL(0.150 ns) = 7.519 ns; Loc. = LCCOMB_X28_Y33_N26; Fanout = 2; COMB Node = 'fulladder:I2\|S'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.398 ns" { fulladder:I1|Cout~9 fulladder:I2|S } "NODE_NAME" } } { "../Fulladder/Fulladder.vhd" "" { Text "C:/altera/81/quartus/Xiuh/Fulladder/Fulladder.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.420 ns) 8.205 ns fulladder:I5\|Cout~7 4 COMB LCCOMB_X28_Y33_N2 2 " "Info: 4: + IC(0.266 ns) + CELL(0.420 ns) = 8.205 ns; Loc. = LCCOMB_X28_Y33_N2; Fanout = 2; COMB Node = 'fulladder:I5\|Cout~7'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.686 ns" { fulladder:I2|S fulladder:I5|Cout~7 } "NODE_NAME" } } { "../Fulladder/Fulladder.vhd" "" { Text "C:/altera/81/quartus/Xiuh/Fulladder/Fulladder.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.459 ns) + CELL(0.438 ns) 9.102 ns fulladder:I6\|S 5 COMB LCCOMB_X29_Y33_N18 2 " "Info: 5: + IC(0.459 ns) + CELL(0.438 ns) = 9.102 ns; Loc. = LCCOMB_X29_Y33_N18; Fanout = 2; COMB Node = 'fulladder:I6\|S'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.897 ns" { fulladder:I5|Cout~7 fulladder:I6|S } "NODE_NAME" } } { "../Fulladder/Fulladder.vhd" "" { Text "C:/altera/81/quartus/Xiuh/Fulladder/Fulladder.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.258 ns) + CELL(0.419 ns) 9.779 ns fulladder:I9\|Cout~7 6 COMB LCCOMB_X29_Y33_N20 2 " "Info: 6: + IC(0.258 ns) + CELL(0.419 ns) = 9.779 ns; Loc. = LCCOMB_X29_Y33_N20; Fanout = 2; COMB Node = 'fulladder:I9\|Cout~7'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.677 ns" { fulladder:I6|S fulladder:I9|Cout~7 } "NODE_NAME" } } { "../Fulladder/Fulladder.vhd" "" { Text "C:/altera/81/quartus/Xiuh/Fulladder/Fulladder.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.278 ns) + CELL(0.437 ns) 10.494 ns fulladder:I10\|Cout~7 7 COMB LCCOMB_X29_Y33_N2 2 " "Info: 7: + IC(0.278 ns) + CELL(0.437 ns) = 10.494 ns; Loc. = LCCOMB_X29_Y33_N2; Fanout = 2; COMB Node = 'fulladder:I10\|Cout~7'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.715 ns" { fulladder:I9|Cout~7 fulladder:I10|Cout~7 } "NODE_NAME" } } { "../Fulladder/Fulladder.vhd" "" { Text "C:/altera/81/quartus/Xiuh/Fulladder/Fulladder.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.262 ns) + CELL(0.419 ns) 11.175 ns fulladder:I11\|Cout~7 8 COMB LCCOMB_X29_Y33_N12 1 " "Info: 8: + IC(0.262 ns) + CELL(0.419 ns) = 11.175 ns; Loc. = LCCOMB_X29_Y33_N12; Fanout = 1; COMB Node = 'fulladder:I11\|Cout~7'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.681 ns" { fulladder:I10|Cout~7 fulladder:I11|Cout~7 } "NODE_NAME" } } { "../Fulladder/Fulladder.vhd" "" { Text "C:/altera/81/quartus/Xiuh/Fulladder/Fulladder.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.620 ns) + CELL(2.828 ns) 14.623 ns R\[6\] 9 PIN PIN_J10 0 " "Info: 9: + IC(0.620 ns) + CELL(2.828 ns) = 14.623 ns; Loc. = PIN_J10; Fanout = 0; PIN Node = 'R\[6\]'" { } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.448 ns" { fulladder:I11|Cout~7 R[6] } "NODE_NAME" } } { "MultBCD.vhd" "" { Text "C:/altera/81/quartus/Xiuh/MultBCD/MultBCD.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.111 ns ( 41.79 % ) " "Info: Total cell delay = 6.111 ns ( 41.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.512 ns ( 58.21 % ) " "Info: Total interconnect delay = 8.512 ns ( 58.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "14.623 ns" { B[1] fulladder:I1|Cout~9 fulladder:I2|S fulladder:I5|Cout~7 fulladder:I6|S fulladder:I9|Cout~7 fulladder:I10|Cout~7 fulladder:I11|Cout~7 R[6] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "14.623 ns" { B[1] {} B[1]~combout {} fulladder:I1|Cout~9 {} fulladder:I2|S {} fulladder:I5|Cout~7 {} fulladder:I6|S {} fulladder:I9|Cout~7 {} fulladder:I10|Cout~7 {} fulladder:I11|Cout~7 {} R[6] {} } { 0.000ns 0.000ns 6.121ns 0.248ns 0.266ns 0.459ns 0.258ns 0.278ns 0.262ns 0.620ns } { 0.000ns 0.850ns 0.150ns 0.150ns 0.420ns 0.438ns 0.419ns 0.437ns 0.419ns 2.828ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "129 " "Info: Peak virtual memory: 129 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 30 14:12:19 2009 " "Info: Processing ended: Thu Apr 30 14:12:19 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 4 s " "Info: Quartus II Full Compilation was successful. 0 errors, 4 warnings" { } { } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
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