multbcd.vhd.bak

Multiplier BCD - vhdl

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.All;

entity MultBCD is
		port( A, B : in std_logic_vector(3 downto 0);
				R : out std_logic_vector(7 downto 0));
	end MultBCD;
		
architecture Arq of MultBCD is
			
			component Halfadder is
					port( A,B : in std_logic;
						S, Cout : out std_logic);
			end component Halfadder;
			
			
			component Fulladder is
					port(A, B, Cin : in std_logic;
						S, Cout : out std_logic);
			end component Fulladder;
			
	
	
			signal AB00,AB10,AB20,AB30, AB01,AB11,AB21,AB31, AB02,AB12,AB22,AB32, AB03,AB13,AB23,AB33 : std_logic;
			signal Link1st : std_logic_vector (6 downto 0);
			signal Link2nd : std_logic_vector (6 downto 0);
			signal Link3rd : std_logic_vector (2 downto 0);
			
			
		begin
		
			AB00<= A(0) and B(0);
			AB10<= A(1) and B(0);
			AB20<= A(2) and B(0);
			AB30<= A(3) and B(0);
			
			AB01<= A(0) and B(1);
			AB11<= A(1) and B(1);
			AB21<= A(2) and B(1);
			AB31<= A(3) and B(1);
			
			AB02<= A(0) and B(2);
			AB12<= A(1) and B(2);
			AB22<= A(2) and B(2);
			AB32<= A(3) and B(2);
			
			AB03<= A(0) and B(3);
			AB13<= A(1) and B(3);
			AB23<= A(2) and B(3);
			AB33<= A(3) and B(3);
			
			R(0) <= AB00;
			
			I0:Halfadder port map (AB10, AB01, R(1), Link1st(0));
			I1:Fulladder port map (AB20, AB11, Link1st(0), Link1st(2), Link1st(1));
			I2:Fulladder port map (AB30, AB21, Link1st(1), Link1st(4), Link1st(3));
			I3:Halfadder port map (Link1st(3), AB31, Link1st(6), Link1st(5));
			
			I4:Halfadder port map (Link1st(2), AB02, R(2), Link2nd(0));
			I5:Fulladder port map (Link1st(4), AB12, Link2nd(0), Link2nd(2), Link2nd(1));
			I6:Fulladder port map (Link1st(6), AB22, Link2nd(1), Link2nd(4), Link2nd(3));
			I7:Fulladder port map (Link1st(5), AB32, Link2nd(3), Link2nd(6), Link2nd(5));
			
			I8:Halfadder port map (Link2nd(2), AB03, R(3), Link3rd(0));
			I9:Fulladder port map (Link2nd(4), AB13, Link3rd(0), R(4), Link3rd(1));
			I10:Fulladder port map (Link2nd(6), AB23, Link3rd(1), R(5), Link3rd(2));
			I11:Fulladder port map (Link2nd(5), AB33, Link3rd(2), R(7), R(8));
			
end Arq;