📄 multbcd.sim.rpt
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; |MultBCD|halfadder:I4|s ; |MultBCD|halfadder:I4|s ; combout ;
; |MultBCD|halfadder:I8|s ; |MultBCD|halfadder:I8|s ; combout ;
; |MultBCD|R[2] ; |MultBCD|R[2] ; padio ;
; |MultBCD|R[3] ; |MultBCD|R[3] ; padio ;
; |MultBCD|R[4] ; |MultBCD|R[4] ; padio ;
; |MultBCD|A[1] ; |MultBCD|A[1]~corein ; combout ;
; |MultBCD|A[2] ; |MultBCD|A[2]~corein ; combout ;
; |MultBCD|A[3] ; |MultBCD|A[3]~corein ; combout ;
+----------------------------+----------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-------------------------------+-------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------+-------------------------------+------------------+
; |MultBCD|AB00~0 ; |MultBCD|AB00~0 ; combout ;
; |MultBCD|halfadder:I0|s ; |MultBCD|halfadder:I0|s ; combout ;
; |MultBCD|AB02 ; |MultBCD|AB02 ; combout ;
; |MultBCD|AB12 ; |MultBCD|AB12 ; combout ;
; |MultBCD|AB30 ; |MultBCD|AB30 ; combout ;
; |MultBCD|fulladder:I1|Cout~8 ; |MultBCD|fulladder:I1|Cout~8 ; combout ;
; |MultBCD|fulladder:I1|Cout~9 ; |MultBCD|fulladder:I1|Cout~9 ; combout ;
; |MultBCD|AB03 ; |MultBCD|AB03 ; combout ;
; |MultBCD|fulladder:I2|Cout~8 ; |MultBCD|fulladder:I2|Cout~8 ; combout ;
; |MultBCD|fulladder:I5|Cout~7 ; |MultBCD|fulladder:I5|Cout~7 ; combout ;
; |MultBCD|AB13 ; |MultBCD|AB13 ; combout ;
; |MultBCD|halfadder:I3|cout ; |MultBCD|halfadder:I3|cout ; combout ;
; |MultBCD|fulladder:I6|Cout~7 ; |MultBCD|fulladder:I6|Cout~7 ; combout ;
; |MultBCD|fulladder:I7|S ; |MultBCD|fulladder:I7|S ; combout ;
; |MultBCD|fulladder:I9|Cout~7 ; |MultBCD|fulladder:I9|Cout~7 ; combout ;
; |MultBCD|fulladder:I10|S ; |MultBCD|fulladder:I10|S ; combout ;
; |MultBCD|fulladder:I7|Cout~7 ; |MultBCD|fulladder:I7|Cout~7 ; combout ;
; |MultBCD|fulladder:I10|Cout~7 ; |MultBCD|fulladder:I10|Cout~7 ; combout ;
; |MultBCD|fulladder:I11|Cout~7 ; |MultBCD|fulladder:I11|Cout~7 ; combout ;
; |MultBCD|fulladder:I11|S~13 ; |MultBCD|fulladder:I11|S~13 ; combout ;
; |MultBCD|R[0] ; |MultBCD|R[0] ; padio ;
; |MultBCD|R[1] ; |MultBCD|R[1] ; padio ;
; |MultBCD|R[5] ; |MultBCD|R[5] ; padio ;
; |MultBCD|R[6] ; |MultBCD|R[6] ; padio ;
; |MultBCD|R[7] ; |MultBCD|R[7] ; padio ;
; |MultBCD|B[0] ; |MultBCD|B[0]~corein ; combout ;
; |MultBCD|A[0] ; |MultBCD|A[0]~corein ; combout ;
; |MultBCD|B[1] ; |MultBCD|B[1]~corein ; combout ;
; |MultBCD|B[2] ; |MultBCD|B[2]~corein ; combout ;
; |MultBCD|B[3] ; |MultBCD|B[3]~corein ; combout ;
+-------------------------------+-------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-------------------------------+-------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------+-------------------------------+------------------+
; |MultBCD|AB00~0 ; |MultBCD|AB00~0 ; combout ;
; |MultBCD|halfadder:I0|s ; |MultBCD|halfadder:I0|s ; combout ;
; |MultBCD|AB02 ; |MultBCD|AB02 ; combout ;
; |MultBCD|AB12 ; |MultBCD|AB12 ; combout ;
; |MultBCD|AB30 ; |MultBCD|AB30 ; combout ;
; |MultBCD|fulladder:I1|Cout~8 ; |MultBCD|fulladder:I1|Cout~8 ; combout ;
; |MultBCD|fulladder:I1|Cout~9 ; |MultBCD|fulladder:I1|Cout~9 ; combout ;
; |MultBCD|AB03 ; |MultBCD|AB03 ; combout ;
; |MultBCD|fulladder:I2|Cout~8 ; |MultBCD|fulladder:I2|Cout~8 ; combout ;
; |MultBCD|fulladder:I5|Cout~7 ; |MultBCD|fulladder:I5|Cout~7 ; combout ;
; |MultBCD|AB13 ; |MultBCD|AB13 ; combout ;
; |MultBCD|halfadder:I3|cout ; |MultBCD|halfadder:I3|cout ; combout ;
; |MultBCD|fulladder:I6|Cout~7 ; |MultBCD|fulladder:I6|Cout~7 ; combout ;
; |MultBCD|fulladder:I7|S ; |MultBCD|fulladder:I7|S ; combout ;
; |MultBCD|fulladder:I9|Cout~7 ; |MultBCD|fulladder:I9|Cout~7 ; combout ;
; |MultBCD|fulladder:I10|S ; |MultBCD|fulladder:I10|S ; combout ;
; |MultBCD|fulladder:I7|Cout~7 ; |MultBCD|fulladder:I7|Cout~7 ; combout ;
; |MultBCD|fulladder:I10|Cout~7 ; |MultBCD|fulladder:I10|Cout~7 ; combout ;
; |MultBCD|fulladder:I11|Cout~7 ; |MultBCD|fulladder:I11|Cout~7 ; combout ;
; |MultBCD|fulladder:I11|S~13 ; |MultBCD|fulladder:I11|S~13 ; combout ;
; |MultBCD|R[0] ; |MultBCD|R[0] ; padio ;
; |MultBCD|R[1] ; |MultBCD|R[1] ; padio ;
; |MultBCD|R[5] ; |MultBCD|R[5] ; padio ;
; |MultBCD|R[6] ; |MultBCD|R[6] ; padio ;
; |MultBCD|R[7] ; |MultBCD|R[7] ; padio ;
; |MultBCD|B[0] ; |MultBCD|B[0]~corein ; combout ;
; |MultBCD|A[0] ; |MultBCD|A[0]~corein ; combout ;
; |MultBCD|B[1] ; |MultBCD|B[1]~corein ; combout ;
; |MultBCD|B[2] ; |MultBCD|B[2]~corein ; combout ;
; |MultBCD|B[3] ; |MultBCD|B[3]~corein ; combout ;
+-------------------------------+-------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
Info: Processing started: Fri May 01 00:38:57 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off MultBCD -c MultBCD
Info: Using vector source file "C:/altera/81/quartus/Xiuh/MultBCD/MultBCD.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 33.33 %
Info: Number of transitions in simulation is 860
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 114 megabytes
Info: Processing ended: Fri May 01 00:38:59 2009
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
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