📄 dsp28_ev.c
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//
// TMDX ALPHA RELEASE
// Intended for product evaluation purposes
//
//###########################################################################
//
// FILE: DSP28_Ev.c
//
// TITLE: DSP28 Event Manager Initialization & Support Functions.
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// =====|=============|======|===============================================
// 0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
// 0.56| 20 May 2002 | L.H. | No change
// 0.57| 27 May 2002 | L.H. | No change
//###########################################################################
#include "DSP28_Device.h"
//---------------------------------------------------------------------------
// InitEv:
//---------------------------------------------------------------------------
// This function initializes to a known state.
//
void InitEv(void)
{
// EVA Configure T1PWM, T2PWM, PWM1-PWM6
// Initalize the timers
// Initalize EVA Timer2 做为QEP计数器
EvaRegs.T2PR = 0x803B; // Timer2 period(7FFF+60) Holds the period value of Timer 2counter
EvaRegs.T2CMPR = 0x7FC3; // Timer2 compare(7FFF-60) Holds the compare value of Timer2 counter
EvaRegs.T2CNT = 0x7FFF; // Timer2 counter Holds the instantaneous value of Timer 1 counter
EvaRegs.T2CON.all = 0x9872; //定向增减,允许编码器接口
//Operation is not affected by emulation suspend
//11 Directional-Up/-Down Count Mode
//Input clock prescaler 000 x/1
//Use own TENABLE bit
//Enable timer operations
//Clock source QEP circuit
//Timer compare register reload condition :00 When counter is 0
// Timer compare enable : Enable timer compare operation
//SELT1PR,SELT3PR : Use own period register
/*SELT1PR In the case of EVA, this bit is SELT1PR (Period register select).
When set to 1 in T2CON, the period register of Timer 1 is chosen for Timer 2
also, ignoring the period register of Timer 2. This bit is a reserved bit in
T1CON.*/
EvaRegs.EVAIMRB.bit.T2PINT = 1; // T2周期中断使能
EvaRegs.EVAIFRB.bit.T2PINT = 1; // 擦除EVA中断标志寄存器
EvaRegs.EVAIMRB.bit.T2CINT = 1; //T2比较中断使能
EvaRegs.EVAIFRB.bit.T2CINT = 1; //T2比较中断标志位置位
PieCtrl.PIEACK.all = 0xFFFF; // 扩展中断使能
// TMODE = continuous up/down
// Timer enable
// Timer compare enable
//EvaRegs.T2CON.all = 0x1083;
// Initalize EVB Timer4
//EvbRegs.T4PR = 0x1194; // Timer2 period
//EvbRegs.T4CMPR = 500; // Timer2 compare
//EvbRegs.T4CNT = 0x0000; // Timer2 counter
// TMODE = continuous up/down
// Timer enable
// Timer compare enable
//EvbRegs.T4CON.all = 0x1083;
// Initalize EVA Timer1
EvaRegs.T1PR = 15000; // Timer1 period
EvaRegs.T1CMPR = 3000; // Timer1 compare
EvaRegs.T1CNT = 0x0000; // Timer1 counter
// TMODE = continuous up/down
// Timer enable
// Timer compare enable
EvaRegs.T1CON.all = 0x1042; //Emulation control bits 00 Stop immediately on emulation suspend
//10 Continuous-Up Count Mode
// Input clock prescaler 000 x/1
//Use own TENABLE bit
//Enable timer operations
//Clock source 00 Internal (i.e., HSPCLK)
//Timer compare register reload condition When counter is 0
//Enable timer compare operation
//Use own period register
// Initalize EVB Timer3
EvbRegs.T3PR = 15000; // Timer1 period
EvbRegs.T3CMPR = 3000; // Timer1 compare
EvbRegs.T3CNT = 0x0000; // Timer1 counter
// TMODE = continuous up/down
// Timer enable
// Timer compare enable
EvbRegs.T3CON.all = 0x1042;
// Setup T1PWM and T2PWM
// Drive T1/T2 PWM by compare logic
EvaRegs.GPTCONA.bit.TCOMPOE =1;
// Polarity of GP Timer 1 Compare = Active high
EvaRegs.GPTCONA.bit.T1PIN = 2;
// Polarity of GP Timer 2 Compare = Active high
EvaRegs.GPTCONA.bit.T2PIN = 2;
EvaRegs.GPTCONA.bit.T1TOADC = 2; //周期中断启动ADC
// Enable compare for PWM1-PWM6
EvaRegs.CMPR1 = 3500;//PWM2
EvaRegs.CMPR2 = 3500;
EvaRegs.CMPR3 = 3500;
// Compare action control. Action that takes place
// on a cmpare event
// output pin 1 CMPR1 - active low
// output pin 2 CMPR1 - active low
// output pin 3 CMPR2 - active low
// output pin 4 CMPR2 - active low
// output pin 5 CMPR3 - active low
// output pin 6 CMPR3 - active low
EvaRegs.ACTR.all = 0x0faa;
EvaRegs.DBTCONA.all = 0x0000; // Disable deadband
EvaRegs.COMCONA.all = 0xC600; //1100 0110 0000 0000
// Setup T3PWM and T4PWM
// Drive T3/T4 PWM by compare logic
EvbRegs.GPTCONB.bit.TCOMPOE =1;
// Polarity of GP Timer 1 Compare = Active high
EvbRegs.GPTCONB.bit.T3PIN = 2;
// Polarity of GP Timer 2 Compare = Active high
EvbRegs.GPTCONB.bit.T4PIN = 2;
EvbRegs.GPTCONB.bit.T3TOADC = 2; //周期中断启动ADC
// Enable compare for PWM1-PWM6
EvbRegs.CMPR4 = 3500;
EvbRegs.CMPR5 = 3500;//PWM2
//EvbRegs.CMPR5 = 1500;
//EvbRegs.CMPR6 = 1500;
// Compare action control. Action that takes place
// on a cmpare event
EvbRegs.ACTRB.all = 0x0fff;// active high
EvbRegs.DBTCONB.all = 0x0000; // Disable deadband
EvbRegs.COMCONB.all = 0xc600; //1100 0110 0010 0000
EvaRegs.T1CON.all = 0x1042;
EvbRegs.T3CON.all = 0x1042;
EvaRegs.EXTCONA.bit.INDCOE = 1;
EvaRegs.COMCONA.bit.FCOMPOE =1;
EvaRegs.COMCONA.bit.FCMP1OE = 1;
EvaRegs.COMCONA.bit.FCMP2OE = 1;
EvaRegs.COMCONA.bit.FCMP3OE = 1;
EvbRegs.COMCONB.bit.FCOMPOE = 1;
}
/*
void InitPWMA(void)
{
// EVA PWM初始化,HSPCLK为SYSCLK/10 = 15Mhz
EvaRegs.T1PR = 0xEFFF; // 周期4096us
EvaRegs.T1CNT = 0x0000; // 计数初值为0
EvaRegs.T1CON.all = 0x1042; // 时钟控制,不分频
// Enable compare for PWM1-PWM6
EvaRegs.CMPR1 = 0x7800; // PWM12占空比50%
EvaRegs.CMPR2 = 0x3000; // PWM34占空比20%
EvaRegs.CMPR3 = 0x0000;
EvaRegs.ACTRA.all = 0x0555; // PWM低有效
EvaRegs.DBTCONA.all = 0x0000; // 死区控制无效
EvaRegs.EXTCONA.bit.INDCOE = 1; // 扩展控制寄存器,比较器1,2,3单独使能
EvaRegs.COMCONA.all = 0xA400; // 比较器控制寄存器
EvaRegs.COMCONA.bit.FCMP1OE = 1;
EvaRegs.COMCONA.bit.FCMP2OE = 1;
EvaRegs.COMCONA.bit.FCMP3OE = 1; // CMP1 Enable
StopCmp2(); // CMP23 Disable
StopCmp3();
}
*/
//===========================================================================
// No more.
//===========================================================================
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