vhdl.txt

单片机和FPGA总线接口设计中的FPGA部分的接口定义

LIBRARY IEEE;                     			--MCS251 单片机读/写电路
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MCS_51 IS
PORT(                          --与8031接口的各端口定义
P0: INOUT STD_LOGIC VECTOR (7 DOWNTO 0) ; 		--双向地址/数据口
P2: IN STD LO GIC V ECTOR (7 DOWNTO 0) ;    		--高8位地址线
RD,WR: IN STD_LOGIC; --读、写允许
ALE: IN STD_LOGIC; --地址锁存
READY: IN STD_LOGIC; --待读入数据准备就绪标志位
AD_CS:OUT STD_LOGIC; --A/D 器件片选信号
DATAIN1: IN STD_LOGIC_VECTOR (7 DOWNTO 0) ;
--单片机待读回信号LA TCH1: IN STD LO GIC; 			--读回信号锁存
DATOUT1: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ; 			--锁存输出数据1
DATOUT2:OUT STD_LOGIC VECTOR (7 DOWNTO 0)) ; 			--锁存输出数据2
END ENTITY MCS_51;
ARCHITECTURE ART OF MCS_51 IS
SIGNAL  LATCH_ADDRES: STD_LOGIC_VECTOR (7 DOWNTO 0) ;
SIGNAL  LATCH_OUT1: STD_LOGIC_VECTOR (7 DOWNTO 0) ;
SIGNAL  LATCH_OUT2: STD_LOGIC_VECTOR (7 DOWNTO 0) ;
SIGNAL  LATCH _IN1: STD_LOGIC_VECTOR (7 DOWNTO 0) ;
SIGNAL  WR_ENABLE1: STD_LOGIC;
SIGNAL  WR_ENABLE2: STD_LOGIC;
BEGIN
PROCESS ( AL E ) IS 						--低8 位地址锁存进程
BEGIN
IF ALE’EVENT AND ALE=’0’ THEN		
LATCH_ADDRES<= P0; 						--AL E 的下降沿将P0 口的低8位地址
END IF;     							--锁入锁存器LATCH_ADDRES中
END PROCESS;
PROCESS (P2,LATCH_ADDRES) IS 			--WR 写信号译码进程1
BEGIN
IF (LATCH_ADDRES=”11110101”) AND ( P2 =”01101111”)THEN
WR_ENABLE1<= WR; 						--写允许
ELSE WR_ENABLE1<=’1’; END IF ; 				--写禁止
END PROCESS;
PROCESS(WR_ENABLE1)IS 						--数据写入寄存器1
BEGIN
IF WR_ENABLE1’EVENT AND WR_ENABLE1 =’1’
THEN  LATCH_OUT1<=P0;  END  IF;
END PROCESS;
PROCESS (P2,LATCH_ADDRES) IS 					--WR 写信号译码进程2
BEGIN
IF ( LATCH_ADDRES=“11110011" )AND (P2="00011111") THEN
WR_ENABLE2 = WR; 						--写允许
ELSE WR_ENABLE2<=’1’; END IF; 				--写禁止
END PROCESS;
PROCESS (WR_ENABLE2) IS 					--数据写入寄存器2
BEGIN
IF WR_ENABLE2’EVENT AND WR_ENABLE2=’1’
THEN LATCH_OUT2<=P0; END IF;
END PROCESS;
PROCESS (P2, LATCH_ADDRES,READY,RD ) IS 			--8031对PLD中数据读入进程
BEGIN
IF (LATCH_ADDRES= “01111110”) AND (P2=“10011111”) AND (READY=’1’) 
AND (RD=’0’) THEN
P0<=LATCH_IN1; 							--寄存器中的数据读入P0 口
ELSE P0<= “ZZZZZZZZ”;  END IF ; 				--禁止读数, P0口呈高阻态
END PROCESS;
PROCESS (LATCH1) IS 						--外部数据进入CPLD 进程
BEGIN
IF LATCH1’EVENT  AND  LATCH1=’1’ THEN
LATCH_IN1<= DATAIN1; END IF;
END PROCESS;
PROCESS(ALTCH_ADDRES) IS 					--A/D工作控制片选信号输出进程
BEGIN
IF (LATCH_ADDRES=”00011110”) THEN
AD_CS<=’0’; 							--允许A /D 工作
ELSE AD_CS<=’1’;  END IF;   					--禁止A /D 工作
END PROCESS;
DATOUT1<=LATCH_OUT1; DATOUT2<=LATCH_OUT2;
END  ARCHITECTURE  ART;