counter.txt

多功能秒表：可以顺计时和倒计时的秒表,用三位数码管显示。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
	port(a,b,c,reset,change,start,clk_out:in std_logic;
	     output:out std_logic_vector (11 downto 0);
		 bell1:out std_logic);
end entity;
architecture behav of counter is
  type state_type is (s0,s1,s2,s3,s4,t0,t1,t2,t3,t4,t5,
                      t6,t7,t8,t9,t10,t11,t12,h0);
  signal state:state_type:=h0;
begin
 process (clk_out,reset,change,start)
 variable output1 : std_logic_vector (11 downto 0);
 begin
  if reset = '0' then state <= h0;
  elsif (rising_edge(clk_out))then
   case state is
   when h0=>
    output1 :="000000000000";
    bell1 <='0';
    --if reset = '0' then state<= h0;
    if change = '0' then state <= t0;
    else state <= s0;
    end if;
   when s0 =>
    output1 := "000000000000";
    if start = '1' then state <= s1;
    else state <= s0;
    end if;
   when s1 =>
    output1 := output1 + '1';
    if start= '0' then state <= s2;
    elsif output1 = "100110011001" then state <= s2;
    elsif output1 (7 downto 0) = "10011001" then state <= s3;
    elsif output1 (3 downto 0) = "1001" then state <= s4;
    else state <= s1;
    end if;
   when s2 =>
    --if reset = '0' then state <= h0;
    if start ='0' then state <= s2;
    else state <= s1;
    end if;
   when s3 =>
   output1(11 downto 8) := output1(11 downto 8)+ '1';output1(7 downto 0) := "00000000";
    state <= s1;
   when s4 =>
    output1(7 downto 4) := output1(7 downto 4)+ '1';output1(3 downto 0) := "0000";
    state <= s1;
   when t0 =>
    output1 := "000000000000";
    state <= t1;
   when t1 =>
    if a = '0' then 
     if output1 (3 downto 0) = "1001" then state <= t3; 
     else state <= t2;
     end if;
    elsif b = '0' then 
     if output1 (7 downto 4) = "1001" then state <= t5; 
     else state <= t4;
     end if;
    elsif c = '0' then 
     if output1 (11 downto 8) = "1001" then state <= t7; 
     else state <= t6;
     end if;
    elsif start = '0' then state <= t1;
    else 
       if output1(11 downto 0)="000000000000" then state <= t9;
         elsif output1(7 downto 0)="00000000" then state<=t10;
         elsif output1(3 downto 0)="0000" then state<=t11;
        else state<=t8;
       end if;
   end if;
   when t2 =>
     output1 (3 downto 0) := output1 (3 downto 0) + "0001";
     
     state <=t1;
     
   when t3 =>
     output1 (3 downto 0) := "0000";
     state <= t1;
   when t4 =>
     output1 (7 downto 4) := output1 (7 downto 4)+"0001";
     
     state <=t1;
     
   when t5 =>
     output1 (7 downto 4) := "0000";
     state <=t1;
   when t6 =>
     output1 (11 downto 8) := output1 (11 downto 8) + "0001";
     
     state <= t1;
     
   when t7 =>
     output1 (11 downto 8) := "0000";
     state <= t1;
   when t8 =>
     output1 := output1 - "000000000001";
     if start = '0' then state <= t12;
     elsif output1 = "000000000000" then state <= t9;
     elsif output1 (7 downto 0) = "00000000" then state <= t10;
     elsif output1 (3 downto 0) = "0000" then state <= t11;
     else state <= t8;
     end if;
     
   when t9 =>
     bell1 <= '1';
     --if reset = '1' then state <= t9;
      state <= t9;
     --end if;
   when t10 =>
     output1(7 downto 0) := "10011001";output1(11 downto 8) := output1(11 downto 8)- '1';
     state <= t8;
   when t11 =>
     output1(3 downto 0) := "1001";output1(7 downto 4) := output1(7 downto 4)- '1';
     state <= t8;
   when t12 =>
     if start = '0' then state <= t12;
     else state <= t8;
     end if;
  end case;
 end if;
output <= output1;
end process;
end behav