📄 display.txt
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library ieee;
use ieee.std_logic_1164.all;
entity display is
port(A,B,C:in std_logic_vector(3 downto 0);
BCD:out std_logic_vector(3 downto 0);
lsd:out std_logic_vector(2 downto 0);
clk:in std_logic);
end entity display;
architecture bebav of display is
type state_type is(m0,m1,m2);
signal state:state_type:=m0;
begin
process(clk)
begin
if clk'event and clk='1' then
case state is
when m0 => BCD<=A;
lsd<="001";
state<=m1;
when m1=> BCD<=B;
lsd<="010";
state<=m2;
when m2=> BCD<=C;
lsd<="100";
state<=m0;
end case ;
end if;
end process;
end bebav;
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