first.map.summary

来自「verilog 初学者原代码」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Sat Apr 04 23:17:07 2009
Quartus II Version : 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
Revision Name : first
Top-level Entity Name : first
Family : MAX II
Total logic elements : 0
Total pins : 16
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0