maltblk.xml

扩频接收机设计的部分

<m>
<dspbuilder_info>
	<dspbuilder_version>7.0</dspbuilder_version>
	<dspbuilder_build_number>Build 33</dspbuilder_build_number>
	<dspbuilder_build_date>02/05/2007</dspbuilder_build_date>
	<toplevel_design_name>m</toplevel_design_name>
	<date_stamp>20070510203711</date_stamp>
</dspbuilder_info>
   <block_dspbuilder>
      <db_block>
         <instancename>Output</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>1</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SingleBit</pvalue>
            <pname>nodetype</pname>
            <pvalue>OutputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>1</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Delay2</srcblk>
            <srcport>1</srcport>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>Delay</instancename>
         <sourcename>DelayAlteraBlockSet</sourcename>
         <instancenumber>2</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>depth</pname>
            <pvalue>1</pvalue>
            <pname>clken</pname>
            <pvalue>off</pvalue>
            <pname>MaskValue</pname>
            <pvalue>1</pvalue>
            <pname>sclr</pname>
            <pvalue>on</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>NOTu</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>NOT1</dstblk>
         </port_db>
         <nparameter>5</nparameter>
      </db_block>
      <db_block>
         <instancename>Delay1</instancename>
         <sourcename>DelayAlteraBlockSet</sourcename>
         <instancenumber>3</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>depth</pname>
            <pvalue>2</pvalue>
            <pname>clken</pname>
            <pvalue>off</pvalue>
            <pname>MaskValue</pname>
            <pvalue>1</pvalue>
            <pname>sclr</pname>
            <pvalue>on</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>NOT1</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>2</outportfanout>
            <dstport>1</dstport>
            <dstblk>Delay2</dstblk>
            <dstport>2</dstport>
            <dstblk>XORu</dstblk>
         </port_db>
         <nparameter>5</nparameter>
      </db_block>
      <db_block>
         <instancename>Delay2</instancename>
         <sourcename>DelayAlteraBlockSet</sourcename>
         <instancenumber>4</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>depth</pname>
            <pvalue>7</pvalue>
            <pname>clken</pname>
            <pvalue>off</pvalue>
            <pname>MaskValue</pname>
            <pvalue>1</pvalue>
            <pname>sclr</pname>
            <pvalue>on</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Delay1</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>2</outportfanout>
            <dstport>1</dstport>
            <dstblk>XORu</dstblk>
            <dstport>1</dstport>
            <dstblk>Output</dstblk>
         </port_db>
         <nparameter>5</nparameter>
      </db_block>
      <db_block>
         <instancename>NOTu</instancename>
         <sourcename>LogiBitAlteraBlockSet</sourcename>
         <instancenumber>5</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>Inputs</pname>
            <pvalue>2</pvalue>
            <pname>Operator</pname>
            <pvalue>NOT</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>XORu</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>Delay</dstblk>
         </port_db>
         <nparameter>3</nparameter>
      </db_block>
      <db_block>
         <instancename>NOT1</instancename>
         <sourcename>LogiBitAlteraBlockSet</sourcename>
         <instancenumber>6</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>Inputs</pname>
            <pvalue>2</pvalue>
            <pname>Operator</pname>
            <pvalue>NOT</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Delay</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>Delay1</dstblk>
         </port_db>
         <nparameter>3</nparameter>
      </db_block>
      <db_block>
         <instancename>XORu</instancename>
         <sourcename>LogiBitAlteraBlockSet</sourcename>
         <instancenumber>7</instancenumber>
         <inport>2</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>Inputs</pname>
            <pvalue>2</pvalue>
            <pname>Operator</pname>
            <pvalue>XOR</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Delay2</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>Delay1</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>NOTu</dstblk>
         </port_db>
         <nparameter>3</nparameter>
      </db_block>
   </block_dspbuilder>
<top_sources>
	<library></library>
</top_sources>
   <top_parameters>
      <starttime>0.0</starttime>
      <stoptime>10</stoptime>
      <fixedstep>auto</fixedstep>
      <nsubsystem>0</nsubsystem>
      <nblocks>7</nblocks>
   </top_parameters>
   <top_signalcompiler>
      <family>Cyclone II</family>
      <opt>Balanced</opt>
      <synthtool>Others</synthtool>
      <vstim>on</vstim>
      <SynthAct>None</SynthAct>
      <workdir>D:\my_eda3\m</workdir>
      <Procetype>prod</Procetype>
      <UseReset>on</UseReset>
      <ResetPin>Active High</ResetPin>
      <ClockPin>Output to Pin</ClockPin>
      <ClockPeriod>20</ClockPeriod>
      <UseSignalTap>off</UseSignalTap>
      <CreatePtfFile>off</CreatePtfFile>
      <SignalTapDepth>128</SignalTapDepth>
      <VerilogSupport>off</VerilogSupport>
      <JTAGCable>USB-Blaster [USB-0]</JTAGCable>
      <bContainMegaCoreIpTb>0</bContainMegaCoreIpTb>
   </top_signalcompiler>
</m>