📄 prev_cmp_m_sequence.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register PRBS\[9\] PRBS\[10\] 340.02 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 340.02 MHz between source register \"PRBS\[9\]\" and destination register \"PRBS\[10\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.400 ns + Longest register register " "Info: + Longest register to register delay is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PRBS\[9\] 1 REG LCFF_X44_Y10_N21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X44_Y10_N21; Fanout = 1; REG Node = 'PRBS\[9\]'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PRBS[9] } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.086 ns) + CELL(0.206 ns) 1.292 ns PRBS\[10\]~feeder 2 COMB LCCOMB_X42_Y10_N14 1 " "Info: 2: + IC(1.086 ns) + CELL(0.206 ns) = 1.292 ns; Loc. = LCCOMB_X42_Y10_N14; Fanout = 1; COMB Node = 'PRBS\[10\]~feeder'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.292 ns" { PRBS[9] PRBS[10]~feeder } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.400 ns PRBS\[10\] 3 REG LCFF_X42_Y10_N15 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.400 ns; Loc. = LCFF_X42_Y10_N15; Fanout = 1; REG Node = 'PRBS\[10\]'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { PRBS[10]~feeder PRBS[10] } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 22.43 % ) " "Info: Total cell delay = 0.314 ns ( 22.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.086 ns ( 77.57 % ) " "Info: Total interconnect delay = 1.086 ns ( 77.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { PRBS[9] PRBS[10]~feeder PRBS[10] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { PRBS[9] {} PRBS[10]~feeder {} PRBS[10] {} } { 0.000ns 1.086ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.169 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.169 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.170 ns) 1.170 ns clock 1 CLK PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(1.170 ns) = 1.170 ns; Loc. = PIN_34; Fanout = 1; CLK Node = 'clock'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.427 ns clock~clkctrl 2 COMB CLKCTRL_G3 33 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.427 ns; Loc. = CLKCTRL_G3; Fanout = 33; COMB Node = 'clock~clkctrl'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.666 ns) 3.169 ns PRBS\[10\] 3 REG LCFF_X42_Y10_N15 1 " "Info: 3: + IC(1.076 ns) + CELL(0.666 ns) = 3.169 ns; Loc. = LCFF_X42_Y10_N15; Fanout = 1; REG Node = 'PRBS\[10\]'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.742 ns" { clock~clkctrl PRBS[10] } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.836 ns ( 57.94 % ) " "Info: Total cell delay = 1.836 ns ( 57.94 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.333 ns ( 42.06 % ) " "Info: Total interconnect delay = 1.333 ns ( 42.06 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.169 ns" { clock clock~clkctrl PRBS[10] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.169 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[10] {} } { 0.000ns 0.000ns 0.257ns 1.076ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.170 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.170 ns) 1.170 ns clock 1 CLK PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(1.170 ns) = 1.170 ns; Loc. = PIN_34; Fanout = 1; CLK Node = 'clock'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.427 ns clock~clkctrl 2 COMB CLKCTRL_G3 33 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.427 ns; Loc. = CLKCTRL_G3; Fanout = 33; COMB Node = 'clock~clkctrl'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.666 ns) 3.170 ns PRBS\[9\] 3 REG LCFF_X44_Y10_N21 1 " "Info: 3: + IC(1.077 ns) + CELL(0.666 ns) = 3.170 ns; Loc. = LCFF_X44_Y10_N21; Fanout = 1; REG Node = 'PRBS\[9\]'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.743 ns" { clock~clkctrl PRBS[9] } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.836 ns ( 57.92 % ) " "Info: Total cell delay = 1.836 ns ( 57.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 42.08 % ) " "Info: Total interconnect delay = 1.334 ns ( 42.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clock clock~clkctrl PRBS[9] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[9] {} } { 0.000ns 0.000ns 0.257ns 1.077ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.169 ns" { clock clock~clkctrl PRBS[10] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.169 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[10] {} } { 0.000ns 0.000ns 0.257ns 1.076ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clock clock~clkctrl PRBS[9] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[9] {} } { 0.000ns 0.000ns 0.257ns 1.077ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { PRBS[9] PRBS[10]~feeder PRBS[10] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.400 ns" { PRBS[9] {} PRBS[10]~feeder {} PRBS[10] {} } { 0.000ns 1.086ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.169 ns" { clock clock~clkctrl PRBS[10] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.169 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[10] {} } { 0.000ns 0.000ns 0.257ns 1.076ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clock clock~clkctrl PRBS[9] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[9] {} } { 0.000ns 0.000ns 0.257ns 1.077ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PRBS[10] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { PRBS[10] {} } { } { } "" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "PRBS\[1\] reset clock 4.481 ns register " "Info: tsu for register \"PRBS\[1\]\" (data pin = \"reset\", clock pin = \"clock\") is 4.481 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.691 ns + Longest pin register " "Info: + Longest pin to register delay is 7.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 PIN PIN_194 1 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_194; Fanout = 1; PIN Node = 'reset'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.393 ns) + CELL(0.206 ns) 7.583 ns PRBS~74 2 COMB LCCOMB_X44_Y10_N28 1 " "Info: 2: + IC(6.393 ns) + CELL(0.206 ns) = 7.583 ns; Loc. = LCCOMB_X44_Y10_N28; Fanout = 1; COMB Node = 'PRBS~74'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.599 ns" { reset PRBS~74 } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.691 ns PRBS\[1\] 3 REG LCFF_X44_Y10_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.691 ns; Loc. = LCFF_X44_Y10_N29; Fanout = 1; REG Node = 'PRBS\[1\]'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { PRBS~74 PRBS[1] } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.298 ns ( 16.88 % ) " "Info: Total cell delay = 1.298 ns ( 16.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.393 ns ( 83.12 % ) " "Info: Total interconnect delay = 6.393 ns ( 83.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.691 ns" { reset PRBS~74 PRBS[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.691 ns" { reset {} reset~combout {} PRBS~74 {} PRBS[1] {} } { 0.000ns 0.000ns 6.393ns 0.000ns } { 0.000ns 0.984ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.170 ns) 1.170 ns clock 1 CLK PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(1.170 ns) = 1.170 ns; Loc. = PIN_34; Fanout = 1; CLK Node = 'clock'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.427 ns clock~clkctrl 2 COMB CLKCTRL_G3 33 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.427 ns; Loc. = CLKCTRL_G3; Fanout = 33; COMB Node = 'clock~clkctrl'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.666 ns) 3.170 ns PRBS\[1\] 3 REG LCFF_X44_Y10_N29 1 " "Info: 3: + IC(1.077 ns) + CELL(0.666 ns) = 3.170 ns; Loc. = LCFF_X44_Y10_N29; Fanout = 1; REG Node = 'PRBS\[1\]'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.743 ns" { clock~clkctrl PRBS[1] } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.836 ns ( 57.92 % ) " "Info: Total cell delay = 1.836 ns ( 57.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 42.08 % ) " "Info: Total interconnect delay = 1.334 ns ( 42.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clock clock~clkctrl PRBS[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[1] {} } { 0.000ns 0.000ns 0.257ns 1.077ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.691 ns" { reset PRBS~74 PRBS[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.691 ns" { reset {} reset~combout {} PRBS~74 {} PRBS[1] {} } { 0.000ns 0.000ns 6.393ns 0.000ns } { 0.000ns 0.984ns 0.206ns 0.108ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clock clock~clkctrl PRBS[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[1] {} } { 0.000ns 0.000ns 0.257ns 1.077ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q q~reg0 7.882 ns register " "Info: tco from clock \"clock\" to destination pin \"q\" through register \"q~reg0\" is 7.882 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.170 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.170 ns) 1.170 ns clock 1 CLK PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(1.170 ns) = 1.170 ns; Loc. = PIN_34; Fanout = 1; CLK Node = 'clock'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.427 ns clock~clkctrl 2 COMB CLKCTRL_G3 33 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.427 ns; Loc. = CLKCTRL_G3; Fanout = 33; COMB Node = 'clock~clkctrl'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.666 ns) 3.170 ns q~reg0 3 REG LCFF_X44_Y10_N17 1 " "Info: 3: + IC(1.077 ns) + CELL(0.666 ns) = 3.170 ns; Loc. = LCFF_X44_Y10_N17; Fanout = 1; REG Node = 'q~reg0'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.743 ns" { clock~clkctrl q~reg0 } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.836 ns ( 57.92 % ) " "Info: Total cell delay = 1.836 ns ( 57.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 42.08 % ) " "Info: Total interconnect delay = 1.334 ns ( 42.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clock clock~clkctrl q~reg0 } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clock {} clock~combout {} clock~clkctrl {} q~reg0 {} } { 0.000ns 0.000ns 0.257ns 1.077ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.408 ns + Longest register pin " "Info: + Longest register to pin delay is 4.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LCFF_X44_Y10_N17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X44_Y10_N17; Fanout = 1; REG Node = 'q~reg0'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q~reg0 } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.312 ns) + CELL(3.096 ns) 4.408 ns q 2 PIN PIN_139 0 " "Info: 2: + IC(1.312 ns) + CELL(3.096 ns) = 4.408 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'q'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.408 ns" { q~reg0 q } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 70.24 % ) " "Info: Total cell delay = 3.096 ns ( 70.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.312 ns ( 29.76 % ) " "Info: Total interconnect delay = 1.312 ns ( 29.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.408 ns" { q~reg0 q } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.408 ns" { q~reg0 {} q {} } { 0.000ns 1.312ns } { 0.000ns 3.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clock clock~clkctrl q~reg0 } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clock {} clock~combout {} clock~clkctrl {} q~reg0 {} } { 0.000ns 0.000ns 0.257ns 1.077ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.408 ns" { q~reg0 q } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.408 ns" { q~reg0 {} q {} } { 0.000ns 1.312ns } { 0.000ns 3.096ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "PRBS\[1\] reset clock -4.215 ns register " "Info: th for register \"PRBS\[1\]\" (data pin = \"reset\", clock pin = \"clock\") is -4.215 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.170 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.170 ns) 1.170 ns clock 1 CLK PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(1.170 ns) = 1.170 ns; Loc. = PIN_34; Fanout = 1; CLK Node = 'clock'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.427 ns clock~clkctrl 2 COMB CLKCTRL_G3 33 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.427 ns; Loc. = CLKCTRL_G3; Fanout = 33; COMB Node = 'clock~clkctrl'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clock clock~clkctrl } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.666 ns) 3.170 ns PRBS\[1\] 3 REG LCFF_X44_Y10_N29 1 " "Info: 3: + IC(1.077 ns) + CELL(0.666 ns) = 3.170 ns; Loc. = LCFF_X44_Y10_N29; Fanout = 1; REG Node = 'PRBS\[1\]'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.743 ns" { clock~clkctrl PRBS[1] } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.836 ns ( 57.92 % ) " "Info: Total cell delay = 1.836 ns ( 57.92 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.334 ns ( 42.08 % ) " "Info: Total interconnect delay = 1.334 ns ( 42.08 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clock clock~clkctrl PRBS[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[1] {} } { 0.000ns 0.000ns 0.257ns 1.077ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" { } { { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.691 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 PIN PIN_194 1 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_194; Fanout = 1; PIN Node = 'reset'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.393 ns) + CELL(0.206 ns) 7.583 ns PRBS~74 2 COMB LCCOMB_X44_Y10_N28 1 " "Info: 2: + IC(6.393 ns) + CELL(0.206 ns) = 7.583 ns; Loc. = LCCOMB_X44_Y10_N28; Fanout = 1; COMB Node = 'PRBS~74'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.599 ns" { reset PRBS~74 } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.691 ns PRBS\[1\] 3 REG LCFF_X44_Y10_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.691 ns; Loc. = LCFF_X44_Y10_N29; Fanout = 1; REG Node = 'PRBS\[1\]'" { } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { PRBS~74 PRBS[1] } "NODE_NAME" } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.298 ns ( 16.88 % ) " "Info: Total cell delay = 1.298 ns ( 16.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.393 ns ( 83.12 % ) " "Info: Total interconnect delay = 6.393 ns ( 83.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.691 ns" { reset PRBS~74 PRBS[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.691 ns" { reset {} reset~combout {} PRBS~74 {} PRBS[1] {} } { 0.000ns 0.000ns 6.393ns 0.000ns } { 0.000ns 0.984ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { clock clock~clkctrl PRBS[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.170 ns" { clock {} clock~combout {} clock~clkctrl {} PRBS[1] {} } { 0.000ns 0.000ns 0.257ns 1.077ns } { 0.000ns 1.170ns 0.000ns 0.666ns } "" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.691 ns" { reset PRBS~74 PRBS[1] } "NODE_NAME" } } { "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.691 ns" { reset {} reset~combout {} PRBS~74 {} PRBS[1] {} } { 0.000ns 0.000ns 6.393ns 0.000ns } { 0.000ns 0.984ns 0.206ns 0.108ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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