m_sequence.sim.qmsg

一种m序列扩频接收机设计代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 20 01:01:53 2009 " "Info: Processing started: Mon Apr 20 01:01:53 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off m_sequence -c m_sequence " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off m_sequence -c m_sequence" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "G:/FPGA project/m_sequence/m_sequence.vwf " "Info: Using vector source file \"G:/FPGA project/m_sequence/m_sequence.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "" 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "" 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0 "" 0}
{ "Info" "IPUTIL_EXTERNAL_PUTIL_SAF_WRITTEN" "G:/FPGA project/m_sequence/m_sequence.saf " "Info: Created Signal Activity File G:/FPGA project/m_sequence/m_sequence.saf" {  } {  } 0 0 "Created Signal Activity File %1!s!" 0 0 "" 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "      0.00 % " "Info: Simulation coverage is       0.00 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0 "" 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "0 " "Info: Number of transitions in simulation is 0" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0 "" 0}
{ "Info" "IVDB_VDB_USE_COMPARISON_RULES" "" "Info: Waveform comparison is performed with the following rules" { { "Info" "IVDB_VDB_COMPARISON_RULE_FOR_VALUE" "Match 0 in expected vector source file with values: 0, L, DC in compared vector file " "Info: Match 0 in expected vector source file with values: 0, L, DC in compared vector file" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARISON_RULE_FOR_VALUE" "Match 1 in expected vector source file with values: 1, H, DC in compared vector file " "Info: Match 1 in expected vector source file with values: 1, H, DC in compared vector file" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARISON_RULE_FOR_VALUE" "Match X in expected vector source file with values: X, W, Z, U, DC in compared vector file " "Info: Match X in expected vector source file with values: X, W, Z, U, DC in compared vector file" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARISON_RULE_FOR_VALUE" "Match L in expected vector source file with values: 0, L, DC in compared vector file " "Info: Match L in expected vector source file with values: 0, L, DC in compared vector file" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARISON_RULE_FOR_VALUE" "Match H in expected vector source file with values: 1, H, DC in compared vector file " "Info: Match H in expected vector source file with values: 1, H, DC in compared vector file" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARISON_RULE_FOR_VALUE" "Match W in expected vector source file with values: X, W, Z, U, DC in compared vector file " "Info: Match W in expected vector source file with values: X, W, Z, U, DC in compared vector file" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARISON_RULE_FOR_VALUE" "Match Z in expected vector source file with values: Z, U, DC in compared vector file " "Info: Match Z in expected vector source file with values: Z, U, DC in compared vector file" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARISON_RULE_FOR_VALUE" "Match U in expected vector source file with values: X, W, Z, U, DC in compared vector file " "Info: Match U in expected vector source file with values: X, W, Z, U, DC in compared vector file" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARISON_RULE_FOR_VALUE" "Match DC in expected vector source file with values: 0, 1, X, L, H, W, Z, U, DC in compared vector file " "Info: Match DC in expected vector source file with values: 0, 1, X, L, H, W, Z, U, DC in compared vector file" {  } {  } 0 0 "%1!s!" 0 0 "" 0}  } {  } 0 0 "Waveform comparison is performed with the following rules" 0 0 "" 0}
{ "Info" "IVDB_VDB_COMPARE_SIGNALS_LIST" "" "Info: The following signals will be compared in waveform comparison" { { "Info" "IVDB_VDB_COMPARED_SIGNAL" "clock " "Info: Signal - clock" {  } {  } 0 0 "Signal - %1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARED_SIGNAL" "q " "Info: Signal - q" {  } {  } 0 0 "Signal - %1!s!" 0 0 "" 0} { "Info" "IVDB_VDB_COMPARED_SIGNAL" "reset " "Info: Signal - reset" {  } {  } 0 0 "Signal - %1!s!" 0 0 "" 0}  } {  } 0 0 "The following signals will be compared in waveform comparison" 0 0 "" 0}
{ "Info" "IVDB_VDB_VECTOR_COMPARE_TRIGGER" "input signals in current vector source file " "Info: Waveform comparison is triggered by changes in transitions of input signals in current vector source file" { { "Info" "IVDB_VDB_TRIGGER_SIGNAL" "clock " "Info: Signal - clock used to trigger waveform comparison in current vector source file" {  } {  } 0 0 "Signal - %1!s! used to trigger waveform comparison in current vector source file" 0 0 "" 0} { "Info" "IVDB_VDB_TRIGGER_SIGNAL" "reset " "Info: Signal - reset used to trigger waveform comparison in current vector source file" {  } {  } 0 0 "Signal - %1!s! used to trigger waveform comparison in current vector source file" 0 0 "" 0}  } {  } 0 0 "Waveform comparison is triggered by changes in transitions of %1!s!" 0 0 "" 0}
{ "Error" "EVDB_VDB_COMPARE_SIM_UNSUCCESSFULL" "G:/FPGA project/m_sequence/db/m_sequence.sim.cvwf  (0 ps to 1.0 us)  G:/FPGA project/m_sequence/m_sequence.vwf " "Error: Simulation results from G:/FPGA project/m_sequence/db/m_sequence.sim.cvwf (0 ps to 1.0 us) do not match expected results from vector source file G:/FPGA project/m_sequence/m_sequence.vwf" { { "Error" "EVDB_VDB_COMPARE_SIM_LEVELS_HEADER" "" "Error: Logic level(s) do not match expected level(s)" { { "Error" "EVDB_VDB_COMPARE_SIM_LEVELS_DIFFER" "\[0\] \[0\] q 0 ps " "Error: Logic level \[0\] does not match expected logic level \[0\] for node \"q\" at time 0 ps" {  } { { "f:/altera/72/quartus/bin/Report_Window_02.qrpt" "" { Report "f:/altera/72/quartus/bin/Report_Window_02.qrpt" "Simulator" "" "" "" "" { Waveform "G:/FPGA project/m_sequence/m_sequence.vwf" "q" "0 ps" "0 ps" "G:/FPGA project/m_sequence/db/m_sequence.sim.cvwf" } "" } } { "G:/FPGA project/m_sequence/m_sequence.vwf" "" { Waveform "G:/FPGA project/m_sequence/m_sequence.vwf" "q" "0 ps" "0 ps" "G:/FPGA project/m_sequence/db/m_sequence.sim.cvwf" } }  } 0 0 "Logic level %1!s! does not match expected logic level %2!s! for node \"%3!s!\" at time %4!s!" 0 0 "" 0}  } {  } 0 0 "Logic level(s) do not match expected level(s)" 0 0 "" 0}  } {  } 0 0 "Simulation results from %1!s!%2!s!do not match expected results from vector source file %3!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Simulator 3 s 0 s Quartus II " "Error: Quartus II Simulator was unsuccessful. 3 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Mon Apr 20 01:01:55 2009 " "Error: Processing ended: Mon Apr 20 01:01:55 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}