📄 ideacore1.vhd
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--
-- Title : ideacore
-- Design : newidea
-- Author : rohini
-- Company : barc
--
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--
-- File : ideacore.vhd
-- Generated : Wed May 3 12:03:40 2006
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
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--
-- Description :
--
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--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {ideacore} architecture {ideacore}}
-- to work my ideacore for second time before giving key_inrdy = '1' and second key_in
-- give reset
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity ideacore1 is
port(
key_in : in STD_LOGIC_VECTOR(127 DOWNTO 0); -- input key for encry-decry
key_inrdy : in std_logic;
inputtxt : in STD_LOGIC_VECTOR(63 DOWNTO 0); -- input data to be encry-decry
load : IN STD_LOGIC;
mode : IN STD_LOGIC; -- mode=0 for encryption, mode=1 for decryption
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
outputtxt : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rdy : out std_logic
);
end ideacore1; --enc
--}} End of automatically maintained section
architecture ideacore of ideacore1 is
component newkeyenc is
port(
key_in1 : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
key_inrdy : in std_logic;
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
round : in std_logic_vector(3 downto 0);
key_req : IN STD_LOGIC;
z1_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z2_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z3_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z4_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z5_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z6_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
keyrdy : out std_logic
);
end component ;
component decnewkey is
port(
key_in : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
key_inrdy : in std_logic;
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
round : in std_logic_vector(3 downto 0);
key_req : IN STD_LOGIC;
z1_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z2_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z3_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z4_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z5_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
z6_ns : out STD_LOGIC_VECTOR(15 DOWNTO 0);
keyrdy : out std_logic
);
end component ;
COMPONENT mult_mod IS
PORT(
Xinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Yinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
output : out STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_mod;
type state_type is (idle,keyreq,s1,s2,s3,s4,s5,s6,s7,s8,s9, ready_st); --,s2,s3,s4);
signal state: state_type;
signal z1_s0,z1_s1,z2_s0,z2_s1,z3_s1,z4_s1,z5_s1,z6_s1,z3_s0,z4_s0,z5_s0,z6_s0 : std_logic_vector(15 downto 0);
signal x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,z1,z2,z3,z4,z5,z6,w1,w2,w3,w4,w5,w6 : std_logic_vector(15 downto 0);
signal keyrdy ,key_req,key_reqEnc ,key_reqDec,keyrdyEnc,keyDecrdy: std_logic;
signal round : std_logic_vector(3 downto 0);
signal inputtxt1 : std_logic_vector(63 downto 0);
signal delay_ctr : std_logic_vector(1 downto 0);
signal delay_ctr_of, delay_ctr_on : std_logic;
begin
ideakeyenc : newkeyenc port map(key_in,key_inrdy,clk,reset,round,key_reqEnc ,z1_s0,z2_s0,z3_s0,z4_s0,z5_s0,z6_s0,keyrdyEnc);
mult_modfirst : mult_mod port map(w1,w2,w3);
mult_modsecond : mult_mod port map (w4,w5,w6);
ideakeydec : decnewkey port map(key_in,key_inrdy,clk,reset,round,key_reqDec,z1_s1,z2_s1,z3_s1,z4_s1,z5_s1,z6_s1,keyDecrdy);
z1 <= z1_s0 WHEN (mode = '0') ELSE
z1_s1 WHEN (mode = '1');
z2 <= z2_s0 WHEN (mode = '0') ELSE
z2_s1 WHEN (mode = '1') ;
z3 <= z3_s0 WHEN (mode = '0') ELSE
z3_s1 WHEN (mode = '1');
z4 <= z4_s0 WHEN (mode = '0') ELSE
z4_s1 WHEN (mode = '1');
z5 <= z5_s0 WHEN (mode = '0') ELSE
z5_s1 WHEN (mode = '1');
z6 <= z6_s0 WHEN (mode = '0') ELSE
z6_s1 WHEN (mode = '1');
keyrdy <= keyrdyEnc when mode = '0' else
keyDecrdy when mode = '1' ;
process(clk,reset)
begin
if reset = '0' then
state <= idle ;
round <= "0000"; rdy <= '0';
outputtxt <= X"0000000000000000";
inputtxt1 <= (others => '0');
x1 <= (others =>'0'); x2 <= (others =>'0'); x3 <= (others =>'0');
x4 <= (others =>'0'); x5 <= (others =>'0'); x6 <= (others =>'0');
x7 <= (others =>'0'); x8 <= (others =>'0'); x9 <= (others =>'0');
x10 <= (others =>'0'); x11 <= (others =>'0'); x12 <= (others =>'0');
x13 <= (others =>'0'); x14 <= (others =>'0');
w1 <= (others =>'0'); w2 <= (others =>'0');
w5 <= (others =>'0'); w4 <= (others =>'0');
key_reqEnc <= '0';
key_reqDec <= '0';
elsif clk'event and clk = '1' then
case state is
when idle =>
rdy <= '0';
-- round <= "0000"; rdy <= '0';
-- outputtxt <= X"0000000000000000";
-- x1 <= (others =>'0'); x2 <= (others =>'0'); x3 <= (others =>'0');
-- x4 <= (others =>'0'); x5 <= (others =>'0'); x6 <= (others =>'0');
-- x7 <= (others =>'0'); x8 <= (others =>'0'); x9 <= (others =>'0');
-- x10 <= (others =>'0'); x11 <= (others =>'0'); x12 <= (others =>'0');
-- x13 <= (others =>'0'); x14 <= (others =>'0');
-- w1 <= (others =>'0'); w2 <= (others =>'0');
-- w5 <= (others =>'0'); w4 <= (others =>'0');
-- delay_ctr_on <= '0';
if load = '1' then
--state <= keyreq;
state <= ready_st;
inputtxt1 <= inputtxt;
else state <= idle;
end if;
when ready_st =>
round <= "0000";
outputtxt <= X"0000000000000000";
x1 <= (others =>'0'); x2 <= (others =>'0'); x3 <= (others =>'0');
x4 <= (others =>'0'); x5 <= (others =>'0'); x6 <= (others =>'0');
x7 <= (others =>'0'); x8 <= (others =>'0'); x9 <= (others =>'0');
x10 <= (others =>'0'); x11 <= (others =>'0'); x12 <= (others =>'0');
x13 <= (others =>'0'); x14 <= (others =>'0');
w1 <= (others =>'0'); w2 <= (others =>'0');
w5 <= (others =>'0'); w4 <= (others =>'0');
key_reqEnc <= '0';
key_reqDec <= '0';
delay_ctr_on <= '0';
state <= keyreq;
when keyreq =>
if mode = '0' then -- for enc
key_reqEnc<= '1';
key_reqDec <= '0';
else
key_reqDec <= '1';
key_reqEnc <= '0';
end if;
if keyrdy = '1' then
state <= s1;
key_reqEnc<= '0';
key_reqDec <= '0';
else state <= keyreq;
end if;
when s1 =>
w1 <=z1; w4 <= z4;
if round = "0000" then
w2 <= inputtxt1(63 downto 48);
w5 <= inputtxt1(15 downto 0);
x2 <= inputtxt1(47 DOWNTO 32) + z2;
x3 <= z3 + inputtxt1(31 DOWNTO 16);
elsif(round<"1000") then
w2 <= x11;
w5<=x14;
x2 <= x12 + z2;
x3 <= z3 + x13;
elsif(round="1000") then
w2 <= x11; w5 <=x14;
x2 <= z2 +x13;
x3 <= z3 + x12;
end if;
state <= s2;
when s2=>
if(round <="0111") then
x1<=w3; x4<=w6;
state <= s3;
elsif round = "1000" then
outputtxt <= w3 & x2 & x3 & w6;
--rdy <= '1';
state <= s9;
end if;
-- x1 <= w3; x4 <= w6;
--state <= s3;
when s3=>
x5 <= x1 xor x3; x6 <= x2 xor x4;
state <= s4;
when s4 =>
w1 <= z5; w2 <= x5;
state <= s5;
when s5 =>
x7<= w3;
x8 <= x6 + w3;
state <= s6;
when s6 =>
w1 <= x8 ; w2 <= z6;
-- key_req <= '0';
state <= s7;
when s7 =>
x9<= w3; x10 <= x7 + w3;
state <= s8;
when s8 =>
x11 <= x1 xor x9; x12 <= x3 xor x9;
x13 <= x2 xor x10; x14 <= x10 xor x4;
round <= round + '1';
state <= keyreq;
when s9 =>
rdy <= '1';
-- delay_ctr_on <= '1';
-- if delay_ctr_of = '1' then
-- delay_ctr_on <= '0';
-- state <= idle;
-- end if;
state <= idle;
--state <= final;
--when final =>
--outputtxt <= x11 & x12 & x13 & x14;
--rdy <= '1';
--rou
end case;
end if;
end process;
process(clk, reset)
begin
if reset = '0' then
delay_ctr <= "00";
elsif clk = '1' and clk'event then
if delay_ctr_on = '1' then
delay_ctr <= delay_ctr + '1' ;
end if;
end if;
end process;
delay_ctr_of <= '1' when delay_ctr = "11" else '0';
end ideacore;
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