uart_transmitter.vhd

This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.

--
--  File: c:\my designs\UART_transmitter\SRC\UART_transmitter.VHD
--  created by Design Wizard: 07/14/04 14:03:30
--

--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {UART_transmitter} architecture {UART_transmitter}}

library IEEE;
use IEEE.std_logic_1164.all;

entity UART_transmitter is
	port (
		Bclk: in STD_LOGIC;	
		rst_b: in STD_LOGIC;
		sysclk: in STD_LOGIC;
		TDRE: in STD_LOGIC;
		loadTDR: in STD_LOGIC;
		DBUS: in STD_LOGIC_VECTOR (7 downto 0);
		setTDRE: out STD_LOGIC;
		TxD: out STD_LOGIC;
		TOVR : out STD_LOGIC
	);
end UART_transmitter;

--}} End of automatically maintained section

architecture UART_transmitter of UART_transmitter is

	type stateType is(IDLE, SYNCH, TDATA);
	signal state, nextstate: stateType;
	signal TSR :std_logic_vector(8 downto 0);
	signal TDR :std_logic_vector(7 downto 0);
	signal Bct: integer range 0 to 10;
	signal inc,clr,loadTSR,shftTSR,start:std_logic;
	signal Bclk_rising, Bclk_dlayed:std_logic;
	begin
	TXD<= TSR(0);
	setTDRE<=loadTSR;
	Bclk_rising<= Bclk and (not Bclk_Dlayed);

	Xmit_control: process(state ,TDRE, Bct ,Bclk_rising)
		begin
			inc<='0'; loadTSR<='0'; shftTSR<='0';start<='0';   --clr<='0'; 
			case state is
				when IDLE => 
				--inc<='0'; clr<='0'; loadTSR<='0'; shftTSR<='0';start<='0';
				clr <= '0';
				if(TDRE = '0') then
						loadTSR<='1'; 
						TOVR <= '0';
						nextstate<=SYNCH;
					else
						nextstate<=IDLE ;
					end if;
				when SYNCH =>
				if Bclk_rising='1' then
					start<='1';
					nextstate<=TDATA;
				else 
					nextstate<=SYNCH;
				end if;
				
				when TDATA =>
				if Bclk_rising ='1' then
					--nextstate<=TDATA;
				if (Bct/=9) then
					shftTSR<='1';
					inc<='1';
					nextstate<=TDATA;
				else
					clr<='1';
					nextstate<=IDLE; 
					TOVR <= '1';
				end if;
				end if;
			end case;
		end process;																																																				
		
		
		xmit_update: process (sysclk , rst_b)
		begin
			if(rst_b ='0') then 
				TSR<="111111111";
				state<= IDLE;
				Bct<=0;
				Bclk_Dlayed<='0';
			elsif sysclk'event and sysclk ='1' then
				state<= nextstate;
				if(clr ='1') then 
					Bct <= 0;
				elsif inc ='1' then
					Bct<=Bct+1;
				end if;
				if loadTDR='1' then
					TDR<=DBUS;
				end if;
				if loadTSR='1' then
					TSR<= TDR &'1';
				end if;
				if start='1' then
					TSR(0) <='0';
				end if;
				if shftTSR='1' then
					TSR<='1'& TSR(8 downto 1);
				end if;
				Bclk_Dlayed<=Bclk;
			end if;
		end process;
end UART_transmitter;