kp_uart.vhd

This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.

									  --ports			--signal 
	ID_FRAME_COMP : id_frame1 
								generic map(data_bytes => bytes)
								port map(  sys_clk         => sys_clk,
        								sys_rst         => intrst,
        								init 			=> init1,  --active high
           								m_s 			=> m_s,
       
	       								LCG_out 		=> idin, 
           								lcg_out_rdy 	=> din_rdy,	 --active high
		       
	    								ID_req 			=> id_req,
           								ID_ack 			=> id_ack,
       
								       	ID_out_mk 		=> id_out_mk,
           								ID_out_mk_rdy 	=> id_out_mk_rdy,
       
	       								tx_data 		=> tx_data,
           								tx_Data_rdy 	=> tx_data_rdy,
           								rx_Data 		=> rx_data,
           								rx_data_rdy 	=> rx_data_rdy,
           								tx_busy 		=> tx_busy1, 
		   								dout 			=> dout1,
		   								crc_ok 			=> led11,
										de_sk_out 		=> de_sk,
										de_Sk_rdy		=> de_Sk_rdy,
		   								control_fr_rdy 	=>  control_fr_rdy,
								--		data_fr_rdy 	=> data_fr_rdy,
										voice_fr_rdy 	=> voice_fr_rdy,

										rx_control_fr_ack => rx_control_fr_ack,
									--	rx_data_fr_ack	=> rx_data_fr_ack,
										rx_voice_fr_ack => rx_voice_fr_ack,
										rx_id_rdy_temp => rx_id_rdy_temp,
										temp_rdy => temp_rdy,
										temp_rdy1 => temp_rdy1,
										temp_rdy2 => temp_rdy2, 
										get1 => get,
										CHADDRIN => addr_adc_in,
										ADCCLK => ADCCLK , 
										ALE => ALE, 
										CHADDR => CHADDR, 
										SOC => SOC, 
										EOC => EOC, 
										OE => OE,
										ADCDATAIN => ADCDATAIN,
										CS_bar => CS_bar,
										DI => DI); 
								
										
	DE_SK_UART_comp : de_sk_uart 
	generic map(data_bytes => bytes)
	port map(de_sk_rdy => de_sk_rdy,
			 sys_clk => sys_clk,
			 sys_rst => intrst,
			 de_sk_RX => de_sk_RX,
			 de_sk => de_sk,
			 de_sk_TX => de_sk_TX);
--	de_sk_TX <= Txd1;
--	de_sk_TX <= rxd when m_s = '0' else de_sk_tx1 when m_s = '1';


	HEX_7SEG1:Hex_7seg_decoder
	port map(HexIn => data71, A => a1, B => b1, 	C => c1, 	D => d1, 	E => e1,	F => f1,	G => g1); 

	HEX_7SEG2:Hex_7seg_decoder
	port map(HexIn => data72, A => a2, B => b2, 	C => c2, 	D => d2, 	E => e2,	F => f2,	G => g2); 


	U6_Ring_detect : ring_detect port map(sys_clk, intrst, DRI, RI, Answer_in, RD_dataout, RD_dataoutRdy, RD_txbusy, Buzzerout);


	PULLUP_answer : PULLUP port map(answer_in);
	answer_in <= answer;


	PULLUPdin1 : PULLUP port map(idin(0));
   	PULLUPdin2 : PULLUP port map(idin(1));
   	PULLUPdin3 : PULLUP port map(idin(2));
   	PULLUPdin4 : PULLUP port map(idin(3));
   	PULLUPdin5 : PULLUP port map(idin(4));
   	PULLUPdin6 : PULLUP port map(idin(5));
   	PULLUPdin7 : PULLUP port map(idin(6));
   	PULLUPdin8 : PULLUP port map(idin(7));
	idin <= din;

	PULLUPsc1 : PULLDOWN port map(iSC(0));
	PULLUPsc2 : PULLDOWN port map(iSC(1));
	PULLUPsc3 : PULLDOWN port map(iSC(2));
	PULLUPsc4 : PULLDOWN port map(iSC(3));
	iSC <= SC;

	PULLUPrst : PULLUP port map(intrst);
	intrst <= rstin;  

	PULLUPinit : PULLUP port map(iinit);
	iinit <= init;
	ibsel <= "000";
	isw <= '0';

	PULLUP_ADC_CH0 : PULLUP port map(addr_adc_in(0));
	PULLUP_ADC_CH1 : PULLUP port map(addr_adc_in(1));
	PULLUP_ADC_CH2 : PULLUP port map(addr_adc_in(2));

	addr_adc_in <= CHADDRIN;

	PULLUP_GET : PULLUP port map (get_in);	
	get_in <= data_fr_rdy;
	get <= not get_in;

	DCM_comp : DCM1 port map
		(RST_IN => intrst1,
	     CLKIN_IN => clkin,
	     LOCKED_OUT => irst,
	     CLKDV_OUT => sys_clk,
	     CLKIN_IBUFG_OUT => user_CLKIN_IBUFG_OUT,
	     CLK0_OUT => user_CLK0_OUT);

   intrst1 <=  not intrst;

--	addr_adc_in(0) <= data_fr_rdy;
--	addr_adc_in(1) <= data_fr_rdy;
--	addr_adc_in(2) <= data_fr_rdy;

   TxD <= Txd1;
--	tx_busy1 <= not tx_busy;

	tx_busy1 <= not tx_busy when M_S = '1';
	RD_txbusy <= tx_busy when M_S = '0';


	init1 <= not DCD and m_s;
	process(sys_clk, irst) 
	begin
	if irst = '0' then
		din_rdy <= '0';
	elsif sys_clk'event and sys_clk = '1' then
		din_rdy <= init1;
	end if;
	end process;

	process(irst, sys_clk) 
	begin
	if irst = '0' then
		tdr <= '0';		tdr1 <= '0';
	elsif sys_clk = '0' and sys_clk'event then
		tdr <= tx_data_rdy;		tdr1 <= tdr;
	end if;
	end process;

	process(irst, sys_clk) 
	begin
	if irst = '0' then
		cntr <= "000000";
	elsif sys_clk'event and sys_clk = '1' then
		if tdr_pulse = '1' then
			cntr <= cntr + '1' ;
		end if;
	end if;
	end process;
 --  	m_s <= '1';-- when iinit = '0' else '0' when irst = '0';
	conn_ovr <= '1' when DCD = '0' else '0' when irst = '0';
	chg_7seg <= '1' when id_out_mk_rdy = '1' else '0' when irst = '0';
	tx_data_rdy_pulse <= not tdr and tx_data_rdy;


	tdr_pulse <= not tdr1 and tdr;

	led(0) <= '1' when irst = '0' else '0' when temp_rdy2 = '1';	    -- rx_id_rdy
	led(1) <= '1' when irst = '0' else '0' when temp_rdy1 = '1';	    -- rx_fr_cv_sk_rdy
	led(2) <= '1' when irst = '0' else '0' when id_out_mk_rdy = '1';
	led(3) <= '1' when irst = '0' else '0' when temp_rdy = '1';			--rx_frame_rdy from rx_slip module.

--	led(3) <= DRI;
--	led(0) <= not pulse_ctr(0);
--	led(1) <= not pulse_ctr(1);
--	led(2) <= not pulse_ctr(2);

	process(sys_clk, irst) begin
	if irst = '0' then
		pulse_ctr <= "000";
	elsif sys_clk'event and sys_clk = '0' then
		if Data_bus_rdy = '1' then
			pulse_ctr <= pulse_ctr + '1';
		end if;
	end if;
	end process;


	process(irst, temp_rdy2)
	begin
		if irst = '0' then
			slip_chk_ctr <= "000";
		elsif rising_edge(temp_rdy2) then
			slip_chk_ctr <= slip_chk_ctr + '1' ;
		end if;													   
	end process;

--	process(chg_7seg, rx_data, id_out_mk, rx_Data_rdy) begin
	process(id_out_mk, id_out_mk_rdy)
	begin
	if id_out_mk_rdy = '1' then
		data71 <= id_out_mk(3 downto 0);
		data72 <= id_out_mk(7 downto 4);
	end if;
	end process;


--	process(tx_data_rdy_pulse)
	process(cntr, irst)
	begin
		if irst = '0' then
	--		led(3) <= '1';
		elsif cntr = "000011" then
	--		led(3) <= '0';
		end if;
	end process;
  --		data_bus_rdy <= data_lcd_rdy;
	--	data_bus <= data_lcd;
--	Process(conn_ovr, tdr_pulse,  data_lcd_rdy) begin
--	if conn_ovr = '0' then	
--		data_bus_rdy <= data_lcd_rdy;
--	else	
--		data_bus_rdy <= tdr_pulse;
--	end if;
--	end process;
  --
	--process(conn_ovr, data_lcd, tx_Data) begin
--	if conn_ovr = '0' then
--		data_bus <= data_lcd;
--	else	
--		data_bus <= tx_data;
--	end if;
--	end process;
 ---
	process(sys_clk) 
	begin
		if sys_clk'event and sys_clk = '0' then
			if conn_ovr = '0' and m_s = '1' then
					data_bus <= data_lcd;
			elsif conn_ovr = '0' and M_s = '0' then 
					data_bus <= RD_dataout;
			else	
				data_bus <= tx_data;
			end if;
		end if;
	end process;


	process(sys_clk) 
	begin
		if sys_clk'event and sys_clk = '0' then
			if conn_ovr = '0' and m_s = '1' then
					data_bus_rdy <= data_lcd_rdy;
			elsif conn_ovr = '0' and M_s = '0' then 
					Data_bus_rdy <= RD_DataoutRdy;
			else	
				data_bus_rdy <= tdr_pulse;
			end if;
		end if;
	end process;


end Behavioral;