kp_uart.vhd

This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;


entity kp_uart is
    Port ( SC : in std_logic_vector(3 downto 0);
           row_ip : out std_logic_vector(3 downto 0);
           rstin : in std_logic;
           clkin : in std_logic;
	       TxD : out std_logic;
           RxD : in std_logic;
		   RI: in std_logic;
		   RTS: out std_logic;
		   CTS: in std_logic;
		   DCD: in std_logic;
		   DTR: out std_logic;
		   DSR: in std_logic;
--         Baud_sel : in std_logic_vector(2 downto 0);
           dout : out std_logic_vector(7 downto 0);
           En : out std_logic;
           Rs : out std_logic;
		   rw : out std_logic;
		   init : in std_Logic;
--		   ri1 : in std_logic;
		   a1, b1, c1, d1, e1, f1, g1 : out std_logic;
		   a2, b2, c2, d2, e2, f2, g2 : out std_logic;
		   Din : in std_logic_vector(7 downto 0);
   		   control_fr_rdy : in std_logic;
			data_fr_rdy : in std_logic;
			voice_fr_rdy : in std_logic;

			rx_control_fr_ack : in std_logic;
--			rx_data_fr_ack : in std_logic;
			rx_voice_fr_ack : in std_logic;

		   led : out std_logic_vector(3 downto 0);
		   m_s : in std_Logic;
-- temp uart inteface signal 
			de_sk_TX : out std_logic;
			de_sk_RX : in std_Logic;

	   -- adc releted signals --
			CHADDRIN : in std_logic_vector(2 downto 0);
			ADCCLK : out std_Logic;	  
			ALE : out std_logic;
			CHADDR : out std_logic_vector(2 downto 0);
			SOC : out std_logic;
			EOC : in std_logic;	 
			OE : out std_logic;
			ADCDATAIN : in std_logic_vector(7 downto 0);
			CS_bar : out STD_LOGIC;	   --active low
			DI : out STD_LOGIC_VECTOR(7 downto 0);

		   answer : in std_logic;
		   Buzzerout : out std_logic);
end kp_uart;

architecture Behavioral of kp_uart is

component transmit is
	Port (  data_bus : in std_logic_vector(7 downto 0);	
		data_rdy : in std_Logic;	
		Baud_sel: in STD_LOGIC_VECTOR (2 downto 0);
		sysclk : in std_logic;
		rst_b : in std_logic;
		txd : out std_logic;
		RxD: in std_logic; 
		RI: in std_logic;
		RTS: out std_logic;
		CTS: in std_logic;
--		DCD: in std_logic;
		DTR: out std_logic;
		DSR: in std_logic;
--		ri1:in std_logic;
		data_out : out std_logic_vector(7 downto 0);
		data_out_rdy : out std_logic;
		tx_busy : out std_logic;
		sw : in std_logic
		);
end component;


component kp_lcd is
	port(
		sys_clk 		: 	in STD_LOGIC;
		sys_rst			: 	in STD_LOGIC;

-- LCD INterface signal   .................................
		data_out 		: 	out STD_LOGIC_VECTOR(7 downto 0);
		en 				: 	out STD_LOGIC;
		r_s 			: 	out STD_LOGIC;
		r_w 			: 	out STD_LOGIC;

-- KeyBoard interface..........................................
		SC 				: 	in STD_LOGIC_VECTOR(3 downto 0);
		row_ip 			: 	out STD_LOGIC_VECTOR(3 downto 0);

		dout 			: 	out std_logic_vector(7 downto 0);
		dout_rdy 		: 	out std_logic;
		tx_busy : in std_logic

	);
end component;

component ID_frame1
	generic(data_bytes : integer);
    Port ( sys_clk : in std_logic;
           sys_rst : in std_logic;
           init : in std_logic;
           m_s : in std_logic;
       
	       LCG_out : in std_logic_vector(7 downto 0);
           lcg_out_rdy : in std_logic;
       
	       ID_req : out std_logic;
           ID_ack : out std_logic;
       
	       ID_out_mk : out std_logic_vector(7 downto 0);
           ID_out_mk_rdy : out std_logic;
       
	       tx_data : out std_logic_vector(7 downto 0);
           tx_Data_rdy : out std_logic;
           rx_Data : in std_logic_vector(7 downto 0);
           rx_data_rdy : in std_logic;
           tx_busy : in std_logic;
		   dout : out std_logic_vector(3 downto 0);
		   crc_ok : out std_logic;
			de_sk_out : out std_logic_vector(((data_bytes*8) - 1) downto 0);	  -- using temp for other purpose
			de_sk_rdy : out std_logic;			  --pulse
		    control_fr_rdy : in std_logic;
	--		data_fr_rdy : in std_logic;
			voice_fr_rdy : in std_logic;

			rx_control_fr_ack : in std_logic;
	--		rx_data_fr_ack : in std_logic;
			rx_voice_fr_ack : in std_logic;
			rx_id_rdy_temp : out std_logic; -- temp
			temp_rdy : out std_logic;
			temp_rdy1 :  out std_logic;
			temp_rdy2 : out std_logic;
			
			-- ADC releted signals 
			GET1 : in std_logic;
			CHADDRIN : in std_logic_vector(2 downto 0);
			ADCCLK : out std_Logic;	  
			ALE : out std_logic;
			CHADDR : out std_logic_vector(2 downto 0);
			SOC : out std_logic;
			EOC : in std_logic;	 
			OE : out std_logic;
			ADCDATAIN : in std_logic_vector(7 downto 0);
			CS_bar : out STD_LOGIC;	   --active low
			DI : out STD_LOGIC_VECTOR(7 downto 0));
end component;


component de_sk_uart is
	generic(data_bytes : integer);
	 port(
		 de_sk_rdy : in STD_LOGIC;
		 sys_clk : in STD_LOGIC;
		 sys_rst : in STD_LOGIC;
		 de_sk_RX : in STD_LOGIC;
		 de_sk : in STD_LOGIC_VECTOR(((data_bytes*8) - 1) downto 0);
		 de_sk_TX : out STD_LOGIC
	     );
end component;	


component Hex_7seg_decoder is
	 port(
		 HexIn : in STD_LOGIC_VECTOR(3 downto 0);
		 A : out STD_LOGIC;	  --
		 B : out STD_LOGIC;		--
		 C : out STD_LOGIC;		  --
		 D : out STD_LOGIC;			-- Active low output
		 E : out STD_LOGIC;		  --
		 F : out STD_LOGIC;		--
		 G : out STD_LOGIC	 --
	     );
end component;


component DCM1 is
    port (
        RST_IN : in std_logic;
        CLKIN_IN : in std_logic;
        LOCKED_OUT : out std_logic;
        CLKDV_OUT : out std_logic;
        CLKIN_IBUFG_OUT : out std_logic;
        CLK0_OUT : out std_logic);
end component;


component Ring_detect is
    Port ( sys_clk : in std_logic;
           sys_rst : in std_logic;
           DRI : out std_logic;
		   RI : in std_logic;
           answer : in std_logic;
           Dataout : out std_logic_vector(7 downto 0);
           Dataoutrdy : out std_logic;
           TxBusy : in std_logic;
           Buzzerout : out std_logic);
end component;


	 constant bytes : integer := 32;

	 signal data_lcd : std_logic_vector(7 downto 0);
	 signal data_lcd_rdy : std_logic;
	 signal iSC : std_logic_vector(3 downto 0);
	 signal irst, intrst, intrst1 : std_Logic ;
	 signal iBsel : std_logic_vector(2 downto 0);
	 signal tx_busy, tx_busy1 : std_logic;  
	 signal isw, iri1 : std_logic;
	 signal DCD1, DCD2 : std_logic;
	 signal data_bus : std_Logic_vector(7 downto 0);
	 signal data_bus_rdy : std_Logic;
	 signal tx_data, rx_data, id_out_mk, data7 : std_logic_vector(7 downto 0);
	 signal tx_data_rdy, rx_data_rdy, iinit, init1 : std_logic;
	 signal data71, data72 : std_logic_vector(3 downto 0);
	 signal din_rdy, id_req, id_out_mk_rdy : std_logic;
	 signal init_rising, init_re :std_logic;
	 signal conn_ovr : std_logic;
	 signal tdr, tx_data_rdy_pulse, tdr_pulse, tdr1 : std_logic;
	 signal cntr : std_logic_vector(5 downto 0);
	 signal idin : std_logic_vector(7 downto 0);
	 signal chg_7seg : std_Logic;
	 signal ID_Ack : std_logic;
	 signal dout1 : std_Logic_vector(3 downto 0);
	 signal led11 : std_logic;
	 signal falling_DCD : std_Logic;   
	 signal de_sk_rdy : std_logic;
	 signal	de_sk : std_Logic_vector(((bytes*8) - 1) downto 0); 
	 signal de_sk_TX1 :std_logic;
	 signal rx_id_rdy_temp, temp_rdy, temp_rdy1, temp_rdy2 : std_Logic;

	 signal slip_chk_ctr : std_Logic_vector(2 downto 0);

	 signal user_CLKIN_IBUFG_OUT, user_CLK0_OUT, sys_clk : std_logic;
	 signal txd1: std_logic;
	 signal get_in, get : std_logic;
	 signal addr_adc_in : std_logic_vector(2 downto 0);-- := "000";

	 signal answer_in : std_logic;
	 signal RD_dataout : std_logic_vector(7 downto 0);
	 signal RD_dataoutRdy, RD_TxBusy, DRI : std_logic;
	 signal pulse_ctr : std_logic_vector(2 downto 0);


--	 signal tx_frame_ck_data : std_logic_vector(255 downto 0);
--	 signal tx_frame_ck_rdy : std_logic;

begin
	UARTcmop : transmit port map(data_bus, data_bus_rdy, ibsel, sys_clk, intrst, txd1, rxd, RI,
		RTS, CTS, DTR, DSR, rx_data,rx_data_rdy, tx_busy, isw);
	LCD_KP : kp_lcd port map(sys_clk, intrst, dout, En, rs, rw, iSC, row_ip, data_lcd, data_lcd_rdy, tx_busy);