cpu_test.map.qmsg

用Verilog 编写的8位risc cpu

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 01 10:49:02 2009 " "Info: Processing started: Fri May 01 10:49:02 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cpu_test -c cpu_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu_test -c cpu_test" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_SEARCH_FILE" "cpu_test.v 1 1 " "Warning: Using design file cpu_test.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_test " "Info: Found entity 1: cpu_test" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "max_cycles packed cpu_test.v(305) " "Warning (10227): Verilog HDL Port Declaration warning at cpu_test.v(305): data type declaration for \"max_cycles\" declares packed dimensions but the port declaration declaration does not" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 305 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "max_cycles cpu_test.v(303) " "Info (10151): Verilog HDL Declaration information at cpu_test.v(303): \"max_cycles\" is declared here" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 303 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "num_outputs packed cpu_test.v(225) " "Warning (10227): Verilog HDL Port Declaration warning at cpu_test.v(225): data type declaration for \"num_outputs\" declares packed dimensions but the port declaration declaration does not" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 225 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "num_outputs cpu_test.v(221) " "Info (10151): Verilog HDL Declaration information at cpu_test.v(221): \"num_outputs\" is declared here" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 221 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "num_matches packed cpu_test.v(226) " "Warning (10227): Verilog HDL Port Declaration warning at cpu_test.v(226): data type declaration for \"num_matches\" declares packed dimensions but the port declaration declaration does not" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 226 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "num_matches cpu_test.v(222) " "Info (10151): Verilog HDL Declaration information at cpu_test.v(222): \"num_matches\" is declared here" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 222 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "num_mismatches packed cpu_test.v(227) " "Warning (10227): Verilog HDL Port Declaration warning at cpu_test.v(227): data type declaration for \"num_mismatches\" declares packed dimensions but the port declaration declaration does not" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 227 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "num_mismatches cpu_test.v(223) " "Info (10151): Verilog HDL Declaration information at cpu_test.v(223): \"num_mismatches\" is declared here" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 223 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "inst packed cpu_test.v(465) " "Warning (10227): Verilog HDL Port Declaration warning at cpu_test.v(465): data type declaration for \"inst\" declares packed dimensions but the port declaration declaration does not" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 465 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "inst cpu_test.v(462) " "Info (10151): Verilog HDL Declaration information at cpu_test.v(462): \"inst\" is declared here" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 462 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "opcode packed cpu_test.v(466) " "Warning (10227): Verilog HDL Port Declaration warning at cpu_test.v(466): data type declaration for \"opcode\" declares packed dimensions but the port declaration declaration does not" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 466 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "opcode cpu_test.v(463) " "Info (10151): Verilog HDL Declaration information at cpu_test.v(463): \"opcode\" is declared here" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 463 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "opcode packed cpu_test.v(519) " "Warning (10227): Verilog HDL Port Declaration warning at cpu_test.v(519): data type declaration for \"opcode\" declares packed dimensions but the port declaration declaration does not" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 519 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "opcode cpu_test.v(516) " "Info (10151): Verilog HDL Declaration information at cpu_test.v(516): \"opcode\" is declared here" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 516 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "mnemonic packed cpu_test.v(520) " "Warning (10227): Verilog HDL Port Declaration warning at cpu_test.v(520): data type declaration for \"mnemonic\" declares packed dimensions but the port declaration declaration does not" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 520 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0 -1}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "mnemonic cpu_test.v(517) " "Info (10151): Verilog HDL Declaration information at cpu_test.v(517): \"mnemonic\" is declared here" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 517 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "cpu_test " "Info: Elaborating entity \"cpu_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_IGNORED_SYSTEM_TASK" "cpu_test.v(111) " "Warning (10175): Verilog HDL warning at cpu_test.v(111): ignoring unsupported system task" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 111 0 0 } }  } 0 10175 "Verilog HDL warning at %1!s!: ignoring unsupported system task" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_IGNORED_SYSTEM_TASK" "cpu_test.v(162) " "Warning (10175): Verilog HDL warning at cpu_test.v(162): ignoring unsupported system task" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 162 0 0 } }  } 0 10175 "Verilog HDL warning at %1!s!: ignoring unsupported system task" 0 0 "" 0 -1}
{ "Warning" "WVRFX_VERI_IGNORED_SYSTEM_TASK" "cpu_test.v(165) " "Warning (10175): Verilog HDL warning at cpu_test.v(165): ignoring unsupported system task" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 165 0 0 } }  } 0 10175 "Verilog HDL warning at %1!s!: ignoring unsupported system task" 0 0 "" 0 -1}
{ "Error" "EVRFX_VERI_2114_UNCONVERTED" "1 \$readmemh memory identifier cpu_test.v(166) " "Error (10853): Verilog HDL error at cpu_test.v(166): argument 1 to \$readmemh must be a memory identifier" {  } { { "cpu_test.v" "" { Text "D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v" 166 0 0 } }  } 0 10853 "Verilog HDL error at %4!s!: argument %1!d! to %2!s! must be a %3!s!" 0 0 "" 0 -1}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0 -1}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 12 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 12 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Error: Peak virtual memory: 170 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Error" "EQEXE_END_BANNER_TIME" "Fri May 01 10:49:04 2009 " "Error: Processing ended: Fri May 01 10:49:04 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}