pram.v

来自「用Verilog 编写的8位risc cpu」· Verilog 代码 · 共 32 行

module pram (
   clk,
   address,
   we,
   din,
   dout
);

input		clk;
input [10:0]	address;
input		we;
input [11:0]	din;
output [11:0]	dout;

parameter word_depth = 2048;

reg [10:0]	address_latched;

reg [11:0]	mem[0:word_depth-1];

// latch address
always @(posedge clk)
   address_latched <= address;
   
// read
assign dout = mem[address_latched];

// write
always @(posedge clk)
   if (we) mem[address] <= din;

endmodule