cpu_test.map.summary

用Verilog 编写的8位risc cpu

Analysis & Synthesis Status : Failed - Fri May 01 10:49:04 2009
Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
Revision Name : cpu_test
Top-level Entity Name : cpu_test
Family : Stratix II
Logic utilization : N/A until Partition Merge
    Combinational ALUTs : N/A until Partition Merge
    Dedicated logic registers : N/A until Partition Merge
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total block memory bits : N/A until Partition Merge
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge
Total DLLs : N/A until Partition Merge