risc8.vcd

来自「用Verilog 编写的8位risc cpu」· VCD 代码 · 共 1,002 行 · 第 1/2 页

$scope module idec $end
$var wire 1 n# inst [11] $end
$var wire 1 o# inst [10] $end
$var wire 1 p# inst [9] $end
$var wire 1 q# inst [8] $end
$var wire 1 r# inst [7] $end
$var wire 1 s# inst [6] $end
$var wire 1 t# inst [5] $end
$var wire 1 u# inst [4] $end
$var wire 1 v# inst [3] $end
$var wire 1 w# inst [2] $end
$var wire 1 x# inst [1] $end
$var wire 1 y# inst [0] $end
$var wire 1 e" aluasel [1] $end
$var wire 1 f" aluasel [0] $end
$var wire 1 g" alubsel [1] $end
$var wire 1 h" alubsel [0] $end
$var wire 1 i" aluop [3] $end
$var wire 1 j" aluop [2] $end
$var wire 1 k" aluop [1] $end
$var wire 1 l" aluop [0] $end
$var wire 1 1# wwe $end
$var wire 1 2# fwe $end
$var wire 1 3# zwe $end
$var wire 1 4# cwe $end
$var wire 1 u" bdpol $end
$var wire 1 o" option $end
$var wire 1 p" tris $end
$var reg 15 z# decodes [14:0] $end
$upscope $end
$upscope $end
$scope module pram $end
$var parameter 32 {# word_depth $end
$var wire 1 |# clk $end
$var wire 1 W address [10] $end
$var wire 1 X address [9] $end
$var wire 1 Y address [8] $end
$var wire 1 Z address [7] $end
$var wire 1 [ address [6] $end
$var wire 1 \ address [5] $end
$var wire 1 ] address [4] $end
$var wire 1 ^ address [3] $end
$var wire 1 _ address [2] $end
$var wire 1 ` address [1] $end
$var wire 1 a address [0] $end
$var wire 1 }# we $end
$var wire 1 ~# din [11] $end
$var wire 1 !$ din [10] $end
$var wire 1 "$ din [9] $end
$var wire 1 #$ din [8] $end
$var wire 1 $$ din [7] $end
$var wire 1 %$ din [6] $end
$var wire 1 &$ din [5] $end
$var wire 1 '$ din [4] $end
$var wire 1 ($ din [3] $end
$var wire 1 )$ din [2] $end
$var wire 1 *$ din [1] $end
$var wire 1 +$ din [0] $end
$var wire 1 b dout [11] $end
$var wire 1 c dout [10] $end
$var wire 1 d dout [9] $end
$var wire 1 e dout [8] $end
$var wire 1 f dout [7] $end
$var wire 1 g dout [6] $end
$var wire 1 h dout [5] $end
$var wire 1 i dout [4] $end
$var wire 1 j dout [3] $end
$var wire 1 k dout [2] $end
$var wire 1 l dout [1] $end
$var wire 1 m dout [0] $end
$var reg 11 ,$ address_latched [10:0] $end
$upscope $end
$scope module exp $end
$var wire 1 -$ clk $end
$var wire 1 .$ reset $end
$var reg 8 /$ dds_out [7:0] $end
$var reg 8 0$ expdin [7:0] $end
$var wire 1 v expdout [7] $end
$var wire 1 w expdout [6] $end
$var wire 1 x expdout [5] $end
$var wire 1 y expdout [4] $end
$var wire 1 z expdout [3] $end
$var wire 1 { expdout [2] $end
$var wire 1 | expdout [1] $end
$var wire 1 } expdout [0] $end
$var wire 1 ~ expaddr [6] $end
$var wire 1 !! expaddr [5] $end
$var wire 1 "! expaddr [4] $end
$var wire 1 #! expaddr [3] $end
$var wire 1 $! expaddr [2] $end
$var wire 1 %! expaddr [1] $end
$var wire 1 &! expaddr [0] $end
$var wire 1 '! expread $end
$var wire 1 (! expwrite $end
$var reg 8 1$ ddsstep [7:0] $end
$var reg 1 2$ ctl [0:0] $end
$var reg 10 3$ accum [9:0] $end
$var reg 8 4$ sinout [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#100
$dumpvars
b1010 !
b1010 "
b1 #
b10 $
b11 %
b100 &
b101 '
b110 (
b111 )
b1000 *
b1001 +
b1010 ,
b1011 -
b1100 .
b1101 /
b1110 0
b1111 1
b10000 2
b10001 3
b10010 4
b10011 5
b10100 6
b10101 7
b10110 8
b10111 9
b11000 :
b11001 ;
b11010 <
b11011 =
b11100 >
b11101 ?
b11110 @
b11111 A
b100000 B
b100001 C
b11111111111 n!
b0 o!
b1 p!
b10 q!
b11 r!
b100 s!
b101 t!
b110 u!
b111 v!
b0 w!
b1 x!
b10 y!
b11 z!
b0 {!
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b10 }!
b11 ~!
b0 !"
b1000 ""
b1 #"
b10 $"
b11 %"
b100 &"
b101 '"
b110 ("
b111 )"
b11000 *"
b111111 +"
b1000110 H#
b0 P#
b1000 Q#
b1 R#
b10 S#
b11 T#
b100 U#
b101 V#
b110 W#
b111 X#
b100000000000 {#
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b1010101 F
bx ."
bx 7"
bx 8"
bx 9"
bx :"
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bx >"
bx ?"
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bx A"
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bx J"
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bx M"
bx N"
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bx a"
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bx s"
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bx v"
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bx ##
bx $#
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bx G#
bx i#
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bx ,$
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b1001 Y!
bx Z!
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b0 ]!
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b0 b!
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$end