risc8.vcd

用Verilog 编写的8位risc cpu

$date
	Thu Apr 30 20:34:59 2009
$end
$version
	ModelSim Version 6.4a
$end
$timescale
	10ps
$end
$scope module cpu_test $end
$var parameter 32 ! CLKHI $end
$var parameter 32 " CLKLO $end
$var parameter 32 # NOP $end
$var parameter 32 $ MOVWF $end
$var parameter 32 % CLRW $end
$var parameter 32 & CLRF $end
$var parameter 32 ' SUBWF $end
$var parameter 32 ( DECF $end
$var parameter 32 ) IORWF $end
$var parameter 32 * ANDWF $end
$var parameter 32 + XORWF $end
$var parameter 32 , ADDWF $end
$var parameter 32 - MOVF $end
$var parameter 32 . COMF $end
$var parameter 32 / INCF $end
$var parameter 32 0 DECFSZ $end
$var parameter 32 1 RRF $end
$var parameter 32 2 RLF $end
$var parameter 32 3 SWAPF $end
$var parameter 32 4 INCFSZ $end
$var parameter 32 5 BCF $end
$var parameter 32 6 BSF $end
$var parameter 32 7 BTFSC $end
$var parameter 32 8 BTFSS $end
$var parameter 32 9 OPTION $end
$var parameter 32 : SLEEP $end
$var parameter 32 ; CLRWDT $end
$var parameter 32 < TRIS $end
$var parameter 32 = RETLW $end
$var parameter 32 > CALL $end
$var parameter 32 ? GOTO $end
$var parameter 32 @ MOVLW $end
$var parameter 32 A IORLW $end
$var parameter 32 B ANDLW $end
$var parameter 32 C XORLW $end
$var reg 1 D clk $end
$var reg 1 E reset $end
$var reg 8 F porta [7:0] $end
$var wire 1 G portb [7] $end
$var wire 1 H portb [6] $end
$var wire 1 I portb [5] $end
$var wire 1 J portb [4] $end
$var wire 1 K portb [3] $end
$var wire 1 L portb [2] $end
$var wire 1 M portb [1] $end
$var wire 1 N portb [0] $end
$var wire 1 O portc [7] $end
$var wire 1 P portc [6] $end
$var wire 1 Q portc [5] $end
$var wire 1 R portc [4] $end
$var wire 1 S portc [3] $end
$var wire 1 T portc [2] $end
$var wire 1 U portc [1] $end
$var wire 1 V portc [0] $end
$var wire 1 W pramaddr [10] $end
$var wire 1 X pramaddr [9] $end
$var wire 1 Y pramaddr [8] $end
$var wire 1 Z pramaddr [7] $end
$var wire 1 [ pramaddr [6] $end
$var wire 1 \ pramaddr [5] $end
$var wire 1 ] pramaddr [4] $end
$var wire 1 ^ pramaddr [3] $end
$var wire 1 _ pramaddr [2] $end
$var wire 1 ` pramaddr [1] $end
$var wire 1 a pramaddr [0] $end
$var wire 1 b pramdata [11] $end
$var wire 1 c pramdata [10] $end
$var wire 1 d pramdata [9] $end
$var wire 1 e pramdata [8] $end
$var wire 1 f pramdata [7] $end
$var wire 1 g pramdata [6] $end
$var wire 1 h pramdata [5] $end
$var wire 1 i pramdata [4] $end
$var wire 1 j pramdata [3] $end
$var wire 1 k pramdata [2] $end
$var wire 1 l pramdata [1] $end
$var wire 1 m pramdata [0] $end
$var wire 1 n expdin [7] $end
$var wire 1 o expdin [6] $end
$var wire 1 p expdin [5] $end
$var wire 1 q expdin [4] $end
$var wire 1 r expdin [3] $end
$var wire 1 s expdin [2] $end
$var wire 1 t expdin [1] $end
$var wire 1 u expdin [0] $end
$var wire 1 v expdout [7] $end
$var wire 1 w expdout [6] $end
$var wire 1 x expdout [5] $end
$var wire 1 y expdout [4] $end
$var wire 1 z expdout [3] $end
$var wire 1 { expdout [2] $end
$var wire 1 | expdout [1] $end
$var wire 1 } expdout [0] $end
$var wire 1 ~ expaddr [6] $end
$var wire 1 !! expaddr [5] $end
$var wire 1 "! expaddr [4] $end
$var wire 1 #! expaddr [3] $end
$var wire 1 $! expaddr [2] $end
$var wire 1 %! expaddr [1] $end
$var wire 1 &! expaddr [0] $end
$var wire 1 '! expread $end
$var wire 1 (! expwrite $end
$var wire 1 )! debugw [7] $end
$var wire 1 *! debugw [6] $end
$var wire 1 +! debugw [5] $end
$var wire 1 ,! debugw [4] $end
$var wire 1 -! debugw [3] $end
$var wire 1 .! debugw [2] $end
$var wire 1 /! debugw [1] $end
$var wire 1 0! debugw [0] $end
$var wire 1 1! debugpc [10] $end
$var wire 1 2! debugpc [9] $end
$var wire 1 3! debugpc [8] $end
$var wire 1 4! debugpc [7] $end
$var wire 1 5! debugpc [6] $end
$var wire 1 6! debugpc [5] $end
$var wire 1 7! debugpc [4] $end
$var wire 1 8! debugpc [3] $end
$var wire 1 9! debugpc [2] $end
$var wire 1 :! debugpc [1] $end
$var wire 1 ;! debugpc [0] $end
$var wire 1 <! debuginst [11] $end
$var wire 1 =! debuginst [10] $end
$var wire 1 >! debuginst [9] $end
$var wire 1 ?! debuginst [8] $end
$var wire 1 @! debuginst [7] $end
$var wire 1 A! debuginst [6] $end
$var wire 1 B! debuginst [5] $end
$var wire 1 C! debuginst [4] $end
$var wire 1 D! debuginst [3] $end
$var wire 1 E! debuginst [2] $end
$var wire 1 F! debuginst [1] $end
$var wire 1 G! debuginst [0] $end
$var wire 1 H! debugstatus [7] $end
$var wire 1 I! debugstatus [6] $end
$var wire 1 J! debugstatus [5] $end
$var wire 1 K! debugstatus [4] $end
$var wire 1 L! debugstatus [3] $end
$var wire 1 M! debugstatus [2] $end
$var wire 1 N! debugstatus [1] $end
$var wire 1 O! debugstatus [0] $end
$var wire 1 P! dds_out [7] $end
$var wire 1 Q! dds_out [6] $end
$var wire 1 R! dds_out [5] $end
$var wire 1 S! dds_out [4] $end
$var wire 1 T! dds_out [3] $end
$var wire 1 U! dds_out [2] $end
$var wire 1 V! dds_out [1] $end
$var wire 1 W! dds_out [0] $end
$var event 1 X! ENDSIM $end
$scope task capture_data $end
$upscope $end
$scope task reset_pic $end
$upscope $end
$scope task drive_clock $end
$upscope $end
$scope task basic $end
$var integer 32 Y! num_outputs $end
$var integer 32 Z! num_matches $end
$var integer 32 [! num_mismatches $end
$upscope $end
$scope task basic_monitor_output_signature $end
$var integer 32 \! num_outputs $end
$var integer 32 ]! num_matches $end
$var integer 32 ^! num_mismatches $end
$var integer 32 _! i $end
$var reg 8 `! expected_output [7:0] $end
$upscope $end
$scope task basic_drive_porta $end
$upscope $end
$scope task dds_test $end
$upscope $end
$scope task monitor_cycles $end
$var integer 32 a! max_cycles $end
$var integer 32 b! cycles $end
$upscope $end
$scope task monitor_rom $end
$upscope $end
$scope task monitor_porta $end
$var reg 8 c! last_porta [7:0] $end
$upscope $end
$scope task monitor_portb $end
$var reg 8 d! last_portb [7:0] $end
$upscope $end
$scope task monitor_portc $end
$var reg 8 e! last_portc [7:0] $end
$upscope $end
$scope task monitor_w $end
$var reg 8 f! last_w [7:0] $end
$upscope $end
$scope task monitor_pc $end
$upscope $end
$scope task monitor_inst $end
$var reg 12 g! last_pc [11:0] $end
$var integer 32 h! opcode $end
$var reg 64 i! mnemonic [63:0] $end
$upscope $end
$scope task lookup_opcode $end
$var reg 12 j! inst [11:0] $end
$var integer 32 k! opcode $end
$upscope $end
$scope task lookup_mnemonic $end
$var integer 32 l! opcode $end
$var reg 64 m! mnemonic [63:0] $end
$upscope $end
$scope module cpu $end
$var parameter 11 n! RESET_VECTOR $end
$var parameter 3 o! INDF_ADDRESS $end
$var parameter 3 p! TMR0_ADDRESS $end
$var parameter 3 q! PCL_ADDRESS $end
$var parameter 3 r! STATUS_ADDRESS $end
$var parameter 3 s! FSR_ADDRESS $end
$var parameter 3 t! PORTA_ADDRESS $end
$var parameter 3 u! PORTB_ADDRESS $end
$var parameter 3 v! PORTC_ADDRESS $end
$var parameter 2 w! ALUASEL_W $end
$var parameter 2 x! ALUASEL_SBUS $end
$var parameter 2 y! ALUASEL_K $end
$var parameter 2 z! ALUASEL_BD $end
$var parameter 2 {! ALUBSEL_W $end
$var parameter 2 |! ALUBSEL_SBUS $end
$var parameter 2 }! ALUBSEL_K $end
$var parameter 2 ~! ALUBSEL_1 $end
$var parameter 4 !" ALUOP_ADD $end
$var parameter 4 "" ALUOP_SUB $end
$var parameter 4 #" ALUOP_AND $end
$var parameter 4 $" ALUOP_OR $end
$var parameter 4 %" ALUOP_XOR $end
$var parameter 4 &" ALUOP_COM $end
$var parameter 4 '" ALUOP_ROR $end
$var parameter 4 (" ALUOP_ROL $end
$var parameter 4 )" ALUOP_SWAP $end
$var parameter 8 *" STATUS_RESET_VALUE $end
$var parameter 8 +" OPTION_RESET_VALUE $end
$var wire 1 ," clk $end
$var wire 1 -" reset $end
$var reg 11 ." paddr [10:0] $end
$var wire 1 b pdata [11] $end
$var wire 1 c pdata [10] $end
$var wire 1 d pdata [9] $end
$var wire 1 e pdata [8] $end
$var wire 1 f pdata [7] $end
$var wire 1 g pdata [6] $end
$var wire 1 h pdata [5] $end
$var wire 1 i pdata [4] $end
$var wire 1 j pdata [3] $end
$var wire 1 k pdata [2] $end
$var wire 1 l pdata [1] $end
$var wire 1 m pdata [0] $end
$var wire 1 /" portain [7] $end
$var wire 1 0" portain [6] $end
$var wire 1 1" portain [5] $end
$var wire 1 2" portain [4] $end
$var wire 1 3" portain [3] $end
$var wire 1 4" portain [2] $end
$var wire 1 5" portain [1] $end
$var wire 1 6" portain [0] $end
$var reg 8 7" portbout [7:0] $end
$var reg 8 8" portcout [7:0] $end
$var wire 1 n expdin [7] $end
$var wire 1 o expdin [6] $end
$var wire 1 p expdin [5] $end
$var wire 1 q expdin [4] $end
$var wire 1 r expdin [3] $end
$var wire 1 s expdin [2] $end
$var wire 1 t expdin [1] $end
$var wire 1 u expdin [0] $end
$var reg 8 9" expdout [7:0] $end
$var reg 7 :" expaddr [6:0] $end
$var reg 1 ;" expread $end
$var reg 1 <" expwrite $end
$var wire 1 )! debugw [7] $end
$var wire 1 *! debugw [6] $end
$var wire 1 +! debugw [5] $end
$var wire 1 ,! debugw [4] $end
$var wire 1 -! debugw [3] $end
$var wire 1 .! debugw [2] $end
$var wire 1 /! debugw [1] $end
$var wire 1 0! debugw [0] $end
$var wire 1 1! debugpc [10] $end
$var wire 1 2! debugpc [9] $end
$var wire 1 3! debugpc [8] $end
$var wire 1 4! debugpc [7] $end
$var wire 1 5! debugpc [6] $end
$var wire 1 6! debugpc [5] $end
$var wire 1 7! debugpc [4] $end
$var wire 1 8! debugpc [3] $end
$var wire 1 9! debugpc [2] $end
$var wire 1 :! debugpc [1] $end
$var wire 1 ;! debugpc [0] $end
$var wire 1 <! debuginst [11] $end
$var wire 1 =! debuginst [10] $end
$var wire 1 >! debuginst [9] $end
$var wire 1 ?! debuginst [8] $end
$var wire 1 @! debuginst [7] $end
$var wire 1 A! debuginst [6] $end
$var wire 1 B! debuginst [5] $end
$var wire 1 C! debuginst [4] $end
$var wire 1 D! debuginst [3] $end
$var wire 1 E! debuginst [2] $end
$var wire 1 F! debuginst [1] $end
$var wire 1 G! debuginst [0] $end
$var wire 1 H! debugstatus [7] $end
$var wire 1 I! debugstatus [6] $end
$var wire 1 J! debugstatus [5] $end
$var wire 1 K! debugstatus [4] $end
$var wire 1 L! debugstatus [3] $end
$var wire 1 M! debugstatus [2] $end
$var wire 1 N! debugstatus [1] $end
$var wire 1 O! debugstatus [0] $end
$var reg 12 =" inst [11:0] $end
$var reg 11 >" pc [10:0] $end
$var reg 11 ?" pc_in [10:0] $end
$var reg 2 @" stacklevel [1:0] $end
$var reg 11 A" stack1 [10:0] $end
$var reg 11 B" stack2 [10:0] $end
$var reg 8 C" w [7:0] $end
$var reg 8 D" status [7:0] $end
$var reg 8 E" fsr [7:0] $end
$var reg 8 F" tmr0 [7:0] $end
$var reg 8 G" prescaler [7:0] $end
$var reg 8 H" option [7:0] $end
$var reg 8 I" trisa [7:0] $end
$var reg 8 J" trisb [7:0] $end
$var reg 8 K" trisc [7:0] $end
$var reg 8 L" porta [7:0] $end
$var reg 8 M" portb [7:0] $end
$var reg 8 N" portc [7:0] $end
$var reg 1 O" skip $end
$var wire 1 P" k [7] $end
$var wire 1 Q" k [6] $end
$var wire 1 R" k [5] $end
$var wire 1 S" k [4] $end
$var wire 1 T" k [3] $end
$var wire 1 U" k [2] $end
$var wire 1 V" k [1] $end
$var wire 1 W" k [0] $end
$var wire 1 X" fsel [4] $end
$var wire 1 Y" fsel [3] $end
$var wire 1 Z" fsel [2] $end
$var wire 1 [" fsel [1] $end
$var wire 1 \" fsel [0] $end
$var wire 1 ]" d $end
$var wire 1 ^" b [2] $end
$var wire 1 _" b [1] $end
$var wire 1 `" b [0] $end
$var reg 7 a" fileaddr [6:0] $end
$var reg 1 b" specialsel $end
$var reg 1 c" regfilesel $end
$var reg 1 d" expsel $end
$var wire 1 e" aluasel [1] $end
$var wire 1 f" aluasel [0] $end
$var wire 1 g" alubsel [1] $end
$var wire 1 h" alubsel [0] $end
$var wire 1 i" aluop [3] $end
$var wire 1 j" aluop [2] $end
$var wire 1 k" aluop [1] $end
$var wire 1 l" aluop [0] $end
$var wire 1 m" zwe $end
$var wire 1 n" cwe $end
$var wire 1 o" isoption $end
$var wire 1 p" istris $end
$var wire 1 q" fwe $end
$var wire 1 r" wwe $end
$var reg 8 s" bd [7:0] $end
$var reg 8 t" bdec [7:0] $end
$var wire 1 u" bdpol $end
$var reg 8 v" regfilein [7:0] $end
$var wire 1 w" regfileout [7] $end
$var wire 1 x" regfileout [6] $end
$var wire 1 y" regfileout [5] $end
$var wire 1 z" regfileout [4] $end
$var wire 1 {" regfileout [3] $end
$var wire 1 |" regfileout [2] $end
$var wire 1 }" regfileout [1] $end
$var wire 1 ~" regfileout [0] $end
$var reg 1 !# regfilewe $end
$var reg 1 "# regfilere $end
$var reg 8 ## dbus [7:0] $end
$var reg 8 $# sbus [7:0] $end
$var reg 8 %# alua [7:0] $end
$var reg 8 &# alub [7:0] $end
$var wire 1 '# aluout [7] $end
$var wire 1 (# aluout [6] $end
$var wire 1 )# aluout [5] $end
$var wire 1 *# aluout [4] $end
$var wire 1 +# aluout [3] $end
$var wire 1 ,# aluout [2] $end
$var wire 1 -# aluout [1] $end
$var wire 1 .# aluout [0] $end
$var wire 1 /# alucout $end
$var wire 1 0# aluz $end
$var wire 1 1# idecwwe $end
$var wire 1 2# idecfwe $end
$var wire 1 3# ideczwe $end
$var wire 1 4# ideccwe $end
$var reg 64 5# inst_string [63:0] $end
$scope module regs $end
$var wire 1 ," clk $end
$var wire 1 -" reset $end
$var wire 1 6# we $end
$var wire 1 7# re $end
$var wire 1 8# bank [1] $end
$var wire 1 9# bank [0] $end
$var wire 1 :# location [4] $end
$var wire 1 ;# location [3] $end
$var wire 1 <# location [2] $end
$var wire 1 =# location [1] $end
$var wire 1 ># location [0] $end
$var wire 1 ?# din [7] $end
$var wire 1 @# din [6] $end
$var wire 1 A# din [5] $end
$var wire 1 B# din [4] $end
$var wire 1 C# din [3] $end
$var wire 1 D# din [2] $end
$var wire 1 E# din [1] $end
$var wire 1 F# din [0] $end
$var wire 1 w" dout [7] $end
$var wire 1 x" dout [6] $end
$var wire 1 y" dout [5] $end
$var wire 1 z" dout [4] $end
$var wire 1 {" dout [3] $end
$var wire 1 |" dout [2] $end
$var wire 1 }" dout [1] $end
$var wire 1 ~" dout [0] $end
$var reg 7 G# final_address [6:0] $end
$scope module dram $end
$var parameter 32 H# word_depth $end
$var wire 1 ," clk $end
$var wire 1 I# address [6] $end
$var wire 1 J# address [5] $end
$var wire 1 K# address [4] $end
$var wire 1 L# address [3] $end
$var wire 1 M# address [2] $end
$var wire 1 N# address [1] $end
$var wire 1 O# address [0] $end
$var wire 1 6# we $end
$var wire 1 ?# din [7] $end
$var wire 1 @# din [6] $end
$var wire 1 A# din [5] $end
$var wire 1 B# din [4] $end
$var wire 1 C# din [3] $end
$var wire 1 D# din [2] $end
$var wire 1 E# din [1] $end
$var wire 1 F# din [0] $end
$var wire 1 w" dout [7] $end
$var wire 1 x" dout [6] $end
$var wire 1 y" dout [5] $end
$var wire 1 z" dout [4] $end
$var wire 1 {" dout [3] $end
$var wire 1 |" dout [2] $end
$var wire 1 }" dout [1] $end
$var wire 1 ~" dout [0] $end
$upscope $end
$upscope $end
$scope module alu $end
$var parameter 4 P# ALUOP_ADD $end
$var parameter 4 Q# ALUOP_SUB $end
$var parameter 4 R# ALUOP_AND $end
$var parameter 4 S# ALUOP_OR $end
$var parameter 4 T# ALUOP_XOR $end
$var parameter 4 U# ALUOP_COM $end
$var parameter 4 V# ALUOP_ROR $end
$var parameter 4 W# ALUOP_ROL $end
$var parameter 4 X# ALUOP_SWAP $end
$var wire 1 i" op [3] $end
$var wire 1 j" op [2] $end
$var wire 1 k" op [1] $end
$var wire 1 l" op [0] $end
$var wire 1 Y# a [7] $end
$var wire 1 Z# a [6] $end
$var wire 1 [# a [5] $end
$var wire 1 \# a [4] $end
$var wire 1 ]# a [3] $end
$var wire 1 ^# a [2] $end
$var wire 1 _# a [1] $end
$var wire 1 `# a [0] $end
$var wire 1 a# b [7] $end
$var wire 1 b# b [6] $end
$var wire 1 c# b [5] $end
$var wire 1 d# b [4] $end
$var wire 1 e# b [3] $end
$var wire 1 f# b [2] $end
$var wire 1 g# b [1] $end
$var wire 1 h# b [0] $end
$var reg 8 i# y [7:0] $end
$var wire 1 j# cin $end
$var reg 1 k# cout $end
$var reg 1 l# zout $end
$var reg 1 m# addercout $end
$upscope $end