_primary.vhd

用Verilog 编写的8位risc cpu

library verilog;
use verilog.vl_types.all;
entity cpu is
    generic(
        RESET_VECTOR    : integer := 2047;
        INDF_ADDRESS    : integer := 0;
        TMR0_ADDRESS    : integer := 1;
        PCL_ADDRESS     : integer := 2;
        STATUS_ADDRESS  : integer := 3;
        FSR_ADDRESS     : integer := 4;
        PORTA_ADDRESS   : integer := 5;
        PORTB_ADDRESS   : integer := 6;
        PORTC_ADDRESS   : integer := 7;
        ALUASEL_W       : integer := 0;
        ALUASEL_SBUS    : integer := 1;
        ALUASEL_K       : integer := 2;
        ALUASEL_BD      : integer := 3;
        ALUBSEL_W       : integer := 0;
        ALUBSEL_SBUS    : integer := 1;
        ALUBSEL_K       : integer := 2;
        ALUBSEL_1       : integer := 3;
        ALUOP_ADD       : integer := 0;
        ALUOP_SUB       : integer := 8;
        ALUOP_AND       : integer := 1;
        ALUOP_OR        : integer := 2;
        ALUOP_XOR       : integer := 3;
        ALUOP_COM       : integer := 4;
        ALUOP_ROR       : integer := 5;
        ALUOP_ROL       : integer := 6;
        ALUOP_SWAP      : integer := 7;
        STATUS_RESET_VALUE: integer := 24;
        OPTION_RESET_VALUE: integer := 63
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        paddr           : out    vl_logic_vector(10 downto 0);
        pdata           : in     vl_logic_vector(11 downto 0);
        portain         : in     vl_logic_vector(7 downto 0);
        portbout        : out    vl_logic_vector(7 downto 0);
        portcout        : out    vl_logic_vector(7 downto 0);
        expdin          : in     vl_logic_vector(7 downto 0);
        expdout         : out    vl_logic_vector(7 downto 0);
        expaddr         : out    vl_logic_vector(6 downto 0);
        expread         : out    vl_logic;
        expwrite        : out    vl_logic;
        debugw          : out    vl_logic_vector(7 downto 0);
        debugpc         : out    vl_logic_vector(10 downto 0);
        debuginst       : out    vl_logic_vector(11 downto 0);
        debugstatus     : out    vl_logic_vector(7 downto 0)
    );
end cpu;