_info

用Verilog 编写的8位risc cpu

m255
K3
13
cModel Technology
Z0 dD:\Verilog project\related resource\Verilog HDL\Chapter-13\risc
valu
Ijm76G=;hi=`f>eQ1fP5cg2
VQYSnV]oklHDTjDe]KXl>;3
w1187592382
8D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/alu.v
FD:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/alu.v
L0 1
Z1 OV;L;6.4a;39
r1
31
Z2 o-work work -nocovercells -O0
!s100 ANjW0:7K4mHE<5dGhG0R33
!s85 0
vcpu
IE=AO<b?KRKN0CO`U1n^CO0
Vkd7X::;c9fn?zkYU<I4dS2
w1187593215
8D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu.v
FD:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu.v
L0 1
R1
r1
31
R2
!s100 AdRX6SjBG<Cc@3D01m?Xk1
!s85 0
vcpu_test
I0ZWH<74a<;2]9mV[@B:;G0
VB3TVRV<0kfQ5Q:@Rk2bz`2
w1187598210
8D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v
FD:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/cpu_test.v
L0 3
R1
r1
31
R2
!s100 P9Z[hXlV]8hmO76@]_NS_1
!s85 0
vdram
I_P75leN19;nJZ3aMUajQa2
VSIYh;?Hh>^dUfC5]Q522E0
w1187838987
8D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/dram.v
FD:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/dram.v
L0 1
R1
r1
31
R2
!s100 :Q4?NdEUM@A2ZQ603obLj0
!s85 0
vexp
IJoZE1fbUDh4L=^0BMN;X40
V5^5c1XJgfd><`[::_J7?13
w1187839080
8D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/exp.v
FD:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/exp.v
L0 1
R1
r1
31
R2
!s100 4V0dMG2ciz@QaNd5[TToc2
!s85 0
videc
I[RGhHFQ5lz=zOU:Z`b`k^0
V8aEAR=h<?J;?h0Cb6AXi23
w1187593734
8D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/idec.v
FD:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/idec.v
L0 1
R1
r1
31
R2
!s100 elK]j95XQTISjjNzQCGJ=1
!s85 0
vpram
InY_ng>CVA51>hn1ecV:k`3
V9SIR7W1>P2gd5QIm>Uhe:3
w1187838979
8D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/pram.v
FD:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/pram.v
L0 1
R1
r1
31
R2
!s100 JJ>4Y?h2H`E7OgBVJldTU2
!s85 0
vregs
!s100 oHS]1@LW>NmK8G6gQ_aRT1
Ij159kFUhdWZcD8P:g0=bj2
VCOdU:LC9>@OKAI?AY_59e2
w1187839028
8D:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/regs.v
FD:/Verilog project/related resource/Verilog HDL/Chapter-13/risc/regs.v
L0 5
R1
r1
!s85 0
31
R2