vol_table.vhd

a vhdl model to ym2149

-- generated with tablegen by MikeJ
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity vol_table is
  port (
    CLK         : in    std_logic;
    ADDR        : in    std_logic_vector(11 downto 0);
    DATA        : out   std_logic_vector(9 downto 0)
    );
end;

architecture RTL of vol_table is

  function romgen_str2slv (str : string) return std_logic_vector is
    variable result : std_logic_vector (str'length*4-1 downto 0);
  begin
    for i in 0 to str'length-1 loop
      case str(str'high-i) is
        when '0'       => result(i*4+3 downto i*4) := x"0";
        when '1'       => result(i*4+3 downto i*4) := x"1";
        when '2'       => result(i*4+3 downto i*4) := x"2";
        when '3'       => result(i*4+3 downto i*4) := x"3";
        when '4'       => result(i*4+3 downto i*4) := x"4";
        when '5'       => result(i*4+3 downto i*4) := x"5";
        when '6'       => result(i*4+3 downto i*4) := x"6";
        when '7'       => result(i*4+3 downto i*4) := x"7";
        when '8'       => result(i*4+3 downto i*4) := x"8";
        when '9'       => result(i*4+3 downto i*4) := x"9";
        when 'A'       => result(i*4+3 downto i*4) := x"A";
        when 'B'       => result(i*4+3 downto i*4) := x"B";
        when 'C'       => result(i*4+3 downto i*4) := x"C";
        when 'D'       => result(i*4+3 downto i*4) := x"D";
        when 'E'       => result(i*4+3 downto i*4) := x"E";
        when 'F'       => result(i*4+3 downto i*4) := x"F";
        when others => result(i*4+3 downto i*4) := "XXXX";
      end case;
    end loop;
    return result;
  end romgen_str2slv;

  attribute INIT_00 : string;
  attribute INIT_01 : string;
  attribute INIT_02 : string;
  attribute INIT_03 : string;
  attribute INIT_04 : string;
  attribute INIT_05 : string;
  attribute INIT_06 : string;
  attribute INIT_07 : string;
  attribute INIT_08 : string;
  attribute INIT_09 : string;
  attribute INIT_0A : string;
  attribute INIT_0B : string;
  attribute INIT_0C : string;
  attribute INIT_0D : string;
  attribute INIT_0E : string;
  attribute INIT_0F : string;

  component RAMB4_S1
    --pragma translate_off
    generic (
      INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
      INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"
      );
    --pragma translate_on
    port (
      DO    : out std_logic_vector (0 downto 0);
      DI    : in  std_logic_vector (0 downto 0);
      ADDR  : in  std_logic_vector (11 downto 0);
      WE    : in  std_logic;
      EN    : in  std_logic;
      RST   : in  std_logic;
      CLK   : in  std_logic
      );
  end component;

  signal rom_addr : std_logic_vector(11 downto 0);

begin

  p_addr : process(ADDR)
  begin
     rom_addr <= (others => '0');
     rom_addr(11 downto 0) <= ADDR;
  end process;

  rom0 : if true generate
    attribute INIT_00 of inst : label is "A3FF3C09E03755DF43AF510A88509D3598CB92F0A961B34BDC9EB90EBC9EF9B0";
    attribute INIT_01 of inst : label is "D800C6FA0A6395DFAAAF531A6C54157058DB73B4696057CE5C971A5E7C9F388A";
    attribute INIT_02 of inst : label is "6000F915F5986A225C1A2F6F9791E7BDA38FA4709571EB63AD8EC58E9C9EC7B0";
    attribute INIT_03 of inst : label is "1C00040D089C9222A41A4F6F179107B5238B047415602B4A6C97654E1C9F478A";
    attribute INIT_04 of inst : label is "EFFFF40DE8C91B07B42FCB10946EB44AA074A38B8A9F84B5EB68DAB19B60F875";
    attribute INIT_05 of inst : label is "0FFF65D647760C68995AF46E23D44B7042F05F8F359F6BB51C6866716C600075";
    attribute INIT_06 of inst : label is "C800CD56163C1C07D4247FF7249045B027F0448F0D9F67B520687C7254641470";
    attribute INIT_07 of inst : label is "B4007DFAD1438123C92447EF04947DEB47EE65F07DD0626A45972E8D759B150F";
    attribute INIT_08 of inst : label is "4000A1A97389B7E38F201AD0BD60DAB2F5F7B690DBA085CEC0118091B190F08D";
    attribute INIT_09 of inst : label is "3C0036FBD8C6C6582120D59571170ECC45107108681076AE715127114210460C";
    attribute INIT_0A of inst : label is "9400428534F9414305C03FDEE7E0BF0CCE379E1782AF84D2852FE5EDB4F8D0EC";
    attribute INIT_0B of inst : label is "13FF36867E392B873398F6B6FF37BAECDDA8812187CEAE13A9A0F722D637B253";
    attribute INIT_0C of inst : label is "24005466854A113B09F36379249B3DA22B9B4C385D743EE536C7403C7B891E9B";
    attribute INIT_0D of inst : label is "240059E7958A37B44F343F3A3D395F2550FB40F97FFB3EFB06FB790444B963FB";
    attribute INIT_0E of inst : label is "98006ADC7A14CD09F2890774ECAA9486CB4AC4B5865DE475DAA9E570A3829879";
    attribute INIT_0F of inst : label is "BFFF4000BFFFA000A000A000A3FFA3FFA3FFA3FFA3FFA3FFA3FFA3FFA3FFA3FF";
  begin
    inst : ramb4_s1
      --pragma translate_off
      generic map (
        INIT_00 => romgen_str2slv(inst'INIT_00),
        INIT_01 => romgen_str2slv(inst'INIT_01),
        INIT_02 => romgen_str2slv(inst'INIT_02),
        INIT_03 => romgen_str2slv(inst'INIT_03),
        INIT_04 => romgen_str2slv(inst'INIT_04),
        INIT_05 => romgen_str2slv(inst'INIT_05),
        INIT_06 => romgen_str2slv(inst'INIT_06),
        INIT_07 => romgen_str2slv(inst'INIT_07),
        INIT_08 => romgen_str2slv(inst'INIT_08),
        INIT_09 => romgen_str2slv(inst'INIT_09),
        INIT_0A => romgen_str2slv(inst'INIT_0A),
        INIT_0B => romgen_str2slv(inst'INIT_0B),
        INIT_0C => romgen_str2slv(inst'INIT_0C),
        INIT_0D => romgen_str2slv(inst'INIT_0D),
        INIT_0E => romgen_str2slv(inst'INIT_0E),
        INIT_0F => romgen_str2slv(inst'INIT_0F)
        )
      --pragma translate_on
      port map (
        DO   => DATA(0 downto 0),
        DI   => "0",
        ADDR => rom_addr,
        WE   => '0',
        EN   => '1',
        RST  => '0',
        CLK  => CLK
        );
  end generate;
  rom1 : if true generate
    attribute INIT_00 of inst : label is "6000872EB8D53E8A305A5340563544CF31412DCA42242A045945633A5945238A";
    attribute INIT_01 of inst : label is "47FFBA234D6A417567A5AEBFCDCABB358EBEB275FDDA95FAA6B29DC5E6BADD45";
    attribute INIT_02 of inst : label is "DFFFBCD9470DD4AACC4AFD25A1B4A647D245C9CA9634C224F845A7BA9945E58A";
    attribute INIT_03 of inst : label is "BC00472EB0F6BB5593B542DA5E4B59B02DBE363569DA3DFA46B278C566BA1A45";
    attribute INIT_04 of inst : label is "A00048D1AF1D448A6C5A394A222525FA51CA4DBE0345694F3DDA22741DDA6230";
    attribute INIT_05 of inst : label is "5FFFA727786BA8E2B50ACD2441B56ECA134A11BA7645024F29DA463479DA6230";
    attribute INIT_06 of inst : label is "67FFFF27C929788A7C51CD4AC24AE5B591B58E45C1BA89B0B625C1CAD625E9CA";
    attribute INIT_07 of inst : label is "D3FF8F230F95E6556AAEF2A5FDB5E25AAE5A91B5CE4AB3DA89B2BE47C9BED645";
    attribute INIT_08 of inst : label is "A8006F71EFE2176AEB5574757AD5584A224A7FB5745A4E7A31B40E4B31B54E47";
    attribute INIT_09 of inst : label is "F4009EDCA914E972FB55C1354AB53C7962B5594217B57FA5410B6EB4304A0FB9";
    attribute INIT_0A of inst : label is "840016A63AEDCC6AB76A588B6B550B7944B51B4A59A5238A1D5A62A75C5D07A6";
    attribute INIT_0B of inst : label is "EFFFCB58AC12E5EA610DB52B60555D6630DD73AA3564428A7CD50BAA15552E8A";
    attribute INIT_0C of inst : label is "00003C38572CC2EDCDE57E9295F28A14BE0D9A2DDA69E717D0EA99D6A61DB8F2";
    attribute INIT_0D of inst : label is "97FF2C475353AF665F19DB139EEDBCE983EDF3EDB3ED8C128BEDF2E9F412CFED";
    attribute INIT_0E of inst : label is "E800E060F4581E5190AE25D8128C05570E2C756648D135262E8D0BD90953112E";
    attribute INIT_0F of inst : label is "80003FFF7FFF6000600060006000600060006000600060006000600060006000";
  begin
    inst : ramb4_s1
      --pragma translate_off
      generic map (
        INIT_00 => romgen_str2slv(inst'INIT_00),
        INIT_01 => romgen_str2slv(inst'INIT_01),
        INIT_02 => romgen_str2slv(inst'INIT_02),
        INIT_03 => romgen_str2slv(inst'INIT_03),
        INIT_04 => romgen_str2slv(inst'INIT_04),
        INIT_05 => romgen_str2slv(inst'INIT_05),
        INIT_06 => romgen_str2slv(inst'INIT_06),
        INIT_07 => romgen_str2slv(inst'INIT_07),
        INIT_08 => romgen_str2slv(inst'INIT_08),
        INIT_09 => romgen_str2slv(inst'INIT_09),
        INIT_0A => romgen_str2slv(inst'INIT_0A),
        INIT_0B => romgen_str2slv(inst'INIT_0B),
        INIT_0C => romgen_str2slv(inst'INIT_0C),
        INIT_0D => romgen_str2slv(inst'INIT_0D),
        INIT_0E => romgen_str2slv(inst'INIT_0E),
        INIT_0F => romgen_str2slv(inst'INIT_0F)
        )
      --pragma translate_on
      port map (
        DO   => DATA(1 downto 1),
        DI   => "0",
        ADDR => rom_addr,
        WE   => '0',
        EN   => '1',
        RST  => '0',
        CLK  => CLK
        );