keyscan.fit.rpt

增加有去抖模块等的fpga控制矩阵键盘的源代码及RTL级的模块图

; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                           ; Auto                           ; Auto                           ;
; Auto Register Duplication                                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------+
; Incremental Compilation Preservation Summary ;
+-------------------------+--------------------+
; Type                    ; Value              ;
+-------------------------+--------------------+
; Placement               ;                    ;
;     -- Requested        ; 0 / 27 ( 0.00 % )  ;
;     -- Achieved         ; 0 / 27 ( 0.00 % )  ;
;                         ;                    ;
; Routing (by Connection) ;                    ;
;     -- Requested        ; 0 / 0 ( 0.00 % )   ;
;     -- Achieved         ; 0 / 0 ( 0.00 % )   ;
+-------------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                       ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Top            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;          ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+


+--------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                             ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Top            ; 27      ; 0                 ; N/A                     ; Source File       ;
+----------------+---------+-------------------+-------------------------+-------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.pin.


+----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                        ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Total logic elements                        ; 11 / 12,060 ( < 1 % )  ;
;     -- Combinational with no register       ; 0                      ;
;     -- Register only                        ; 0                      ;
;     -- Combinational with a register        ; 11                     ;
;                                             ;                        ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 0                      ;
;     -- 3 input functions                    ; 0                      ;
;     -- 2 input functions                    ; 10                     ;
;     -- 1 input functions                    ; 1                      ;
;     -- 0 input functions                    ; 0                      ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 2                      ;
;     -- arithmetic mode                      ; 9                      ;
;     -- qfbk mode                            ; 0                      ;
;     -- register cascade mode                ; 0                      ;
;     -- synchronous clear/load mode          ; 0                      ;
;     -- asynchronous clear/load mode         ; 11                     ;
;                                             ;                        ;
; Total registers                             ; 11 / 12,567 ( < 1 % )  ;
; Total LABs                                  ; 2 / 1,206 ( < 1 % )    ;
; Logic elements in carry chains              ; 10                     ;
; User inserted logic elements                ; 0                      ;
; Virtual pins                                ; 0                      ;
; I/O pins                                    ; 16 / 173 ( 9 % )       ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )         ;
; Global signals                              ; 2                      ;
; M4Ks                                        ; 0 / 52 ( 0 % )         ;
; Total memory bits                           ; 0 / 239,616 ( 0 % )    ;
; Total RAM block bits                        ; 0 / 239,616 ( 0 % )    ;
; PLLs                                        ; 0 / 2 ( 0 % )          ;
; Global clocks                               ; 2 / 8 ( 25 % )         ;
; JTAGs                                       ; 0 / 1 ( 0 % )          ;