keyscan.tan.rpt

增加有去抖模块等的fpga控制矩阵键盘的源代码及RTL级的模块图

; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[3]  ; clk_block:inst|q[6]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 2.192 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[1]  ; clk_block:inst|q[3]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 2.187 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[0]  ; clk_block:inst|q[5]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 2.181 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[1]  ; clk_block:inst|q[2]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 2.107 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[0]  ; clk_block:inst|q[4]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 2.101 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[7]  ; clk_block:inst|q[10] ; CLK1M      ; CLK1M    ; None                        ; None                      ; 2.051 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[2]  ; clk_block:inst|q[5]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 2.051 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[0]  ; clk_block:inst|q[3]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 2.021 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[8]  ; clk_block:inst|q[10] ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.976 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[3]  ; clk_block:inst|q[5]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.975 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[7]  ; clk_block:inst|q[9]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.971 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[2]  ; clk_block:inst|q[4]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.971 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[6]  ; clk_block:inst|q[10] ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.964 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[4]  ; clk_block:inst|q[10] ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.946 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[4]  ; clk_block:inst|q[9]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.946 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[4]  ; clk_block:inst|q[8]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.946 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[4]  ; clk_block:inst|q[7]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.946 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[4]  ; clk_block:inst|q[6]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.946 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[0]  ; clk_block:inst|q[2]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.941 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[5]  ; clk_block:inst|q[10] ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.929 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[5]  ; clk_block:inst|q[9]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.929 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[5]  ; clk_block:inst|q[8]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.929 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[5]  ; clk_block:inst|q[7]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.929 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[5]  ; clk_block:inst|q[6]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.929 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[8]  ; clk_block:inst|q[9]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.896 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[3]  ; clk_block:inst|q[4]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.895 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[7]  ; clk_block:inst|q[8]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.891 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[2]  ; clk_block:inst|q[3]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.891 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[6]  ; clk_block:inst|q[9]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.884 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[6]  ; clk_block:inst|q[8]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.804 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[9]  ; clk_block:inst|q[10] ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.726 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[4]  ; clk_block:inst|q[5]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.725 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[6]  ; clk_block:inst|q[7]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.724 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[1]  ; clk_block:inst|q[1]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.483 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[0]  ; clk_block:inst|q[1]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.329 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[10] ; clk_block:inst|q[10] ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.273 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[8]  ; clk_block:inst|q[8]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.272 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[3]  ; clk_block:inst|q[3]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.271 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[7]  ; clk_block:inst|q[7]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.267 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[2]  ; clk_block:inst|q[2]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.267 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[9]  ; clk_block:inst|q[9]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.114 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[5]  ; clk_block:inst|q[5]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.114 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[4]  ; clk_block:inst|q[4]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.113 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[6]  ; clk_block:inst|q[6]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.112 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clk_block:inst|q[0]  ; clk_block:inst|q[0]  ; CLK1M      ; CLK1M    ; None                        ; None                      ; 1.014 ns                ;
+-------+------------------------------------------------+----------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------+
; tco                                                                               ;
+-------+--------------+------------+----------------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From                 ; To        ; From Clock ;
+-------+--------------+------------+----------------------+-----------+------------+
; N/A   ; None         ; 8.641 ns   ; clk_block:inst|q[8]  ; SELOUT[0] ; CLK1M      ;
; N/A   ; None         ; 8.158 ns   ; clk_block:inst|q[9]  ; SELOUT[1] ; CLK1M      ;
; N/A   ; None         ; 7.682 ns   ; clk_block:inst|q[10] ; SELOUT[2] ; CLK1M      ;
+-------+--------------+------------+----------------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Thu Apr 23 21:20:01 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off keyscan -c keyscan --timing_analysis_only
Info: Only one processor detected - disabling parallel compilation
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK1M" is an undefined clock
Info: Clock "CLK1M" Internal fmax is restricted to 275.03 MHz between source register "clk_block:inst|q[1]" and destination register "clk_block:inst|q[10]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.560 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y16_N0; Fanout = 3; REG Node = 'clk_block:inst|q[1]'
            Info: 2: + IC(0.745 ns) + CELL(0.564 ns) = 1.309 ns; Loc. = LC_X11_Y16_N0; Fanout = 2; COMB Node = 'clk_block:inst|q[1]~71'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.387 ns; Loc. = LC_X11_Y16_N1; Fanout = 2; COMB Node = 'clk_block:inst|q[2]~69'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.465 ns; Loc. = LC_X11_Y16_N2; Fanout = 2; COMB Node = 'clk_block:inst|q[3]~67'
            Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.543 ns; Loc. = LC_X11_Y16_N3; Fanout = 2; COMB Node = 'clk_block:inst|q[4]~65'
            Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 1.721 ns; Loc. = LC_X11_Y16_N4; Fanout = 5; COMB Node = 'clk_block:inst|q[5]~63'
            Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 2.560 ns; Loc. = LC_X11_Y16_N9; Fanout = 2; REG Node = 'clk_block:inst|q[10]'
            Info: Total cell delay = 1.815 ns ( 70.90 % )
            Info: Total interconnect delay = 0.745 ns ( 29.10 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK1M" to destination register is 3.246 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 11; CLK Node = 'CLK1M'
                Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N9; Fanout = 2; REG Node = 'clk_block:inst|q[10]'
                Info: Total cell delay = 2.180 ns ( 67.16 % )
                Info: Total interconnect delay = 1.066 ns ( 32.84 % )
            Info: - Longest clock path from clock "CLK1M" to source register is 3.246 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 11; CLK Node = 'CLK1M'
                Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N0; Fanout = 3; REG Node = 'clk_block:inst|q[1]'
                Info: Total cell delay = 2.180 ns ( 67.16 % )
                Info: Total interconnect delay = 1.066 ns ( 32.84 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLK1M" to destination pin "SELOUT[0]" through register "clk_block:inst|q[8]" is 8.641 ns
    Info: + Longest clock path from clock "CLK1M" to source register is 3.246 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 11; CLK Node = 'CLK1M'
        Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X11_Y16_N7; Fanout = 4; REG Node = 'clk_block:inst|q[8]'
        Info: Total cell delay = 2.180 ns ( 67.16 % )
        Info: Total interconnect delay = 1.066 ns ( 32.84 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.171 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y16_N7; Fanout = 4; REG Node = 'clk_block:inst|q[8]'
        Info: 2: + IC(3.063 ns) + CELL(2.108 ns) = 5.171 ns; Loc. = PIN_83; Fanout = 0; PIN Node = 'SELOUT[0]'
        Info: Total cell delay = 2.108 ns ( 40.77 % )
        Info: Total interconnect delay = 3.063 ns ( 59.23 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Thu Apr 23 21:20:02 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01