keyscan.map.rpt

增加有去抖模块等的fpga控制矩阵键盘的源代码及RTL级的模块图

+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                            ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+
; keys_decoder.vhd                 ; yes             ; User VHDL File                     ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_decoder.vhd ;
; clk_block.vhd                    ; yes             ; User VHDL File                     ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd    ;
; pre_key.bdf                      ; yes             ; User Block Diagram/Schematic File  ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/pre_key.bdf      ;
; key_dounce4.bdf                  ; yes             ; User Block Diagram/Schematic File  ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/key_dounce4.bdf  ;
; keys_display.vhd                 ; yes             ; User VHDL File                     ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd ;
; keyscan.bdf                      ; yes             ; User Block Diagram/Schematic File  ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf      ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 11    ;
;     -- Combinational with no register       ; 0     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 11    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 0     ;
;     -- 2 input functions                    ; 10    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 2     ;
;     -- arithmetic mode                      ; 9     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 11    ;
;                                             ;       ;
; Total registers                             ; 11    ;
; Total logic cells in carry chains           ; 10    ;
; I/O pins                                    ; 16    ;
; Maximum fan-out node                        ; CLK1M ;
; Maximum fan-out                             ; 11    ;
; Total fan-out                               ; 46    ;
; Average fan-out                             ; 1.70  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name     ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+--------------+
; |keyscan                   ; 11 (0)      ; 11           ; 0           ; 16   ; 0            ; 0 (0)        ; 0 (0)             ; 11 (0)           ; 10 (0)          ; 0 (0)      ; |keyscan                ; work         ;
;    |clk_block:inst|        ; 11 (11)     ; 11           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 11 (11)          ; 10 (10)         ; 0 (0)      ; |keyscan|clk_block:inst ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 11    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 11    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Thu Apr 23 21:19:47 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keyscan -c keyscan
Info: Found 2 design units, including 1 entities, in source file keys_decoder.vhd
    Info: Found design unit 1: keys_decoder-one
    Info: Found entity 1: keys_decoder
Info: Found 2 design units, including 1 entities, in source file clk_block.vhd
    Info: Found design unit 1: clk_block-one
    Info: Found entity 1: clk_block
Info: Found 1 design units, including 1 entities, in source file pre_key.bdf
    Info: Found entity 1: pre_key
Info: Found 1 design units, including 1 entities, in source file key_dounce4.bdf
    Info: Found entity 1: key_dounce4
Info: Found 2 design units, including 1 entities, in source file keys_display.vhd
    Info: Found design unit 1: keys_display-one
    Info: Found entity 1: keys_display
Info: Found 1 design units, including 1 entities, in source file keyscan.bdf
    Info: Found entity 1: keyscan
Info: Elaborating entity "keyscan" for the top level hierarchy
Info: Elaborating entity "keys_display" for hierarchy "keys_display:inst2"
Warning (10541): VHDL Signal Declaration warning at keys_display.vhd(9): used implicit default value for signal "segout" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10036): Verilog HDL or VHDL warning at keys_display.vhd(14): object "seg" assigned a value but never read
Info: Elaborating entity "keys_decoder" for hierarchy "keys_decoder:inst3"
Info: Elaborating entity "clk_block" for hierarchy "clk_block:inst"
Info: Elaborating entity "key_dounce4" for hierarchy "key_dounce4:inst1"
Info: Elaborating entity "pre_key" for hierarchy "key_dounce4:inst1|pre_key:inst"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "SEGOUT[6]" is stuck at GND
    Warning (13410): Pin "SEGOUT[5]" is stuck at GND
    Warning (13410): Pin "SEGOUT[4]" is stuck at GND
    Warning (13410): Pin "SEGOUT[3]" is stuck at GND
    Warning (13410): Pin "SEGOUT[2]" is stuck at GND
    Warning (13410): Pin "SEGOUT[1]" is stuck at GND
    Warning (13410): Pin "SEGOUT[0]" is stuck at GND
Warning: Design contains 4 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "KEY[3]"
    Warning (15610): No output dependent on input pin "KEY[2]"
    Warning (15610): No output dependent on input pin "KEY[1]"
    Warning (15610): No output dependent on input pin "KEY[0]"
Info: Implemented 27 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 10 output pins
    Info: Implemented 11 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
    Info: Peak virtual memory: 174 megabytes
    Info: Processing ended: Thu Apr 23 21:19:51 2009
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:02