keys_decoder.vhd.bak

增加有去抖模块等的fpga控制矩阵键盘的源代码及RTL级的模块图

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity keys_decoder is
port(clk,clr:in std_logic;
	seltmp:in std_logic_vector(2 downto 0);
	key :in std_logic_vector(3 downto 0);
	key_code:out std_logic_vector(4 downto 0));
end keys_decoder;
architecture one of keys_decoder is
signal z:std_logic_vector(6 downto 0);
signal zout:std_logic_vector(4 downto 0);
begin
z<= key & seltmp;
key_code<=zout;
process(clr,clk)
begin
if clr='0' then
zout<=(others=>'0');
elsif clk'event and clk='1' then
case z is
when "1110000" =>zout<="00000";--0
when "1110001" =>zout<="00001";--1
when "1110010" =>zout<="00010";--2
when "1110011" =>zout<="00011";--3
when "1110100" =>zout<="10000";--MEM
when "1110101" =>zout<="10001";--ESC
when "1110110" =>zout<="00100";--4
when "1110111" =>zout<="00101";--5
when "1101000" =>zout<="00110";--6
when "1101001" =>zout<="00111";--7
when "1101010" =>zout<="10010";--REG
when "1101011" =>zout<="10011";--EXEC
when "1101100" =>zout<="01000";--8
when "1101101" =>zout<="01001";--9
when "1101110" =>zout<="01010";--A
when "1101111" =>zout<="01011";--B
when "1011000" =>zout<="10100";--C
when "1011011" =>zout<="01101";--D
when "1011100" =>zout<="01110";--E
when "1011101" =>zout<="01111";--F
when "1011110" =>zout<="10110";--NEXT
when "1011111" =>zout<="10111";--ENTER
when "0111000" =>zout<="11000";--CTRL
when "0111001" =>zout<="11010";--NOP1
when "0111010" =>zout<="11011";--NOP2
when "0111011" =>zout<="11100";--NOP3
when "0111100" =>zout<="11101";--NOP4
when "0111101" =>zout<="11001";--SHIFT
when "0111110" =>zout<="11110";--NC
when "0111111" =>zout<="11110";--NC
when others => null;
end case;
end if;
end one;