prev_cmp_keyscan.map.qmsg

增加有去抖模块等的fpga控制矩阵键盘的源代码及RTL级的模块图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 23 21:18:58 2009 " "Info: Processing started: Thu Apr 23 21:18:58 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off keyscan -c keyscan " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keyscan -c keyscan" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keys_decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file keys_decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 keys_decoder-one " "Info: Found design unit 1: keys_decoder-one" {  } { { "keys_decoder.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_decoder.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 keys_decoder " "Info: Found entity 1: keys_decoder" {  } { { "keys_decoder.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_decoder.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_block.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clk_block.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_block-one " "Info: Found design unit 1: clk_block-one" {  } { { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_block " "Info: Found entity 1: clk_block" {  } { { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pre_key.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pre_key.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pre_key " "Info: Found entity 1: pre_key" {  } { { "pre_key.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/pre_key.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_dounce4.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file key_dounce4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 key_dounce4 " "Info: Found entity 1: key_dounce4" {  } { { "key_dounce4.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/key_dounce4.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keys_display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file keys_display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 keys_display-one " "Info: Found design unit 1: keys_display-one" {  } { { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 keys_display " "Info: Found entity 1: keys_display" {  } { { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keyscan.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file keyscan.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 keyscan " "Info: Found entity 1: keyscan" {  } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "keyscan " "Info: Elaborating entity \"keyscan\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Error" "EGDFX_INCORRECT_PIN_CONNECTOR_STYLE" "KEY\[3..0\] " "Error: Bus name allowed only on bus line -- pin \"KEY\[3..0\]\"" {  } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 56 224 360 "KEY\[3..0\]" "" } } } }  } 0 0 "Bus name allowed only on bus line -- pin \"%1!s!\"" 0 0 "" 0 0}
{ "Error" "EGDFX_INCORRECT_CONNECTOR_STYLE" "K\[3..0\] " "Error: Bus name allowed only on bus line -- signal \"K\[3..0\]\"" {  } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 336 224 296 352 "K\[3..0\]" "" } } } }  } 0 0 "Bus name allowed only on bus line -- signal \"%1!s!\"" 0 0 "" 0 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "173 " "Error: Peak virtual memory: 173 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Thu Apr 23 21:19:00 2009 " "Error: Processing ended: Thu Apr 23 21:19:00 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}