keyscan.fit.qmsg

增加有去抖模块等的fpga控制矩阵键盘的源代码及RTL级的模块图

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.670 ns register register " "Info: Estimated most critical path is register to register delay of 2.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_block:inst\|q\[0\] 1 REG LAB_X10_Y16 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X10_Y16; Fanout = 4; REG Node = 'clk_block:inst\|q\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_block:inst|q[0] } "NODE_NAME" } } { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.575 ns) 1.274 ns clk_block:inst\|q\[1\]~71COUT1_83 2 COMB LAB_X11_Y16 2 " "Info: 2: + IC(0.699 ns) + CELL(0.575 ns) = 1.274 ns; Loc. = LAB_X11_Y16; Fanout = 2; COMB Node = 'clk_block:inst\|q\[1\]~71COUT1_83'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { clk_block:inst|q[0] clk_block:inst|q[1]~71COUT1_83 } "NODE_NAME" } } { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.354 ns clk_block:inst\|q\[2\]~69COUT1_85 3 COMB LAB_X11_Y16 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.354 ns; Loc. = LAB_X11_Y16; Fanout = 2; COMB Node = 'clk_block:inst\|q\[2\]~69COUT1_85'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { clk_block:inst|q[1]~71COUT1_83 clk_block:inst|q[2]~69COUT1_85 } "NODE_NAME" } } { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.434 ns clk_block:inst\|q\[3\]~67COUT1_87 4 COMB LAB_X11_Y16 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.434 ns; Loc. = LAB_X11_Y16; Fanout = 2; COMB Node = 'clk_block:inst\|q\[3\]~67COUT1_87'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { clk_block:inst|q[2]~69COUT1_85 clk_block:inst|q[3]~67COUT1_87 } "NODE_NAME" } } { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.514 ns clk_block:inst\|q\[4\]~65COUT1_89 5 COMB LAB_X11_Y16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.514 ns; Loc. = LAB_X11_Y16; Fanout = 2; COMB Node = 'clk_block:inst\|q\[4\]~65COUT1_89'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { clk_block:inst|q[3]~67COUT1_87 clk_block:inst|q[4]~65COUT1_89 } "NODE_NAME" } } { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.772 ns clk_block:inst\|q\[5\]~63 6 COMB LAB_X11_Y16 5 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.772 ns; Loc. = LAB_X11_Y16; Fanout = 5; COMB Node = 'clk_block:inst\|q\[5\]~63'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { clk_block:inst|q[4]~65COUT1_89 clk_block:inst|q[5]~63 } "NODE_NAME" } } { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.670 ns clk_block:inst\|q\[10\] 7 REG LAB_X11_Y16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.898 ns) = 2.670 ns; Loc. = LAB_X11_Y16; Fanout = 2; REG Node = 'clk_block:inst\|q\[10\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.898 ns" { clk_block:inst|q[5]~63 clk_block:inst|q[10] } "NODE_NAME" } } { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.971 ns ( 73.82 % ) " "Info: Total cell delay = 1.971 ns ( 73.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.699 ns ( 26.18 % ) " "Info: Total interconnect delay = 0.699 ns ( 26.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.670 ns" { clk_block:inst|q[0] clk_block:inst|q[1]~71COUT1_83 clk_block:inst|q[2]~69COUT1_85 clk_block:inst|q[3]~67COUT1_87 clk_block:inst|q[4]~65COUT1_89 clk_block:inst|q[5]~63 clk_block:inst|q[10] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X10_Y14 X20_Y27 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X10_Y14 to location X20_Y27" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "7 " "Warning: Following 7 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEGOUT\[6\] GND " "Info: Pin SEGOUT\[6\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[6] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEGOUT\[5\] GND " "Info: Pin SEGOUT\[5\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[5] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEGOUT\[4\] GND " "Info: Pin SEGOUT\[4\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[4] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEGOUT\[3\] GND " "Info: Pin SEGOUT\[3\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[3] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEGOUT\[2\] GND " "Info: Pin SEGOUT\[2\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[2] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEGOUT\[1\] GND " "Info: Pin SEGOUT\[1\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[1] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SEGOUT\[0\] GND " "Info: Pin SEGOUT\[0\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[0] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.fit.smsg " "Info: Generated suppressed messages file F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "193 " "Info: Peak virtual memory: 193 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 23 21:19:57 2009 " "Info: Processing ended: Thu Apr 23 21:19:57 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}