keyscan.fit.qmsg

增加有去抖模块等的fpga控制矩阵键盘的源代码及RTL级的模块图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 23 21:19:51 2009 " "Info: Processing started: Thu Apr 23 21:19:51 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off keyscan -c keyscan " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off keyscan -c keyscan" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Info: Only one processor detected - disabling parallel compilation" {  } {  } 0 0 "Only one processor detected - disabling parallel compilation" 0 0 "" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "keyscan EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"keyscan\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "2 " "Info: Fitter converted 2 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 24 " "Info: Pin ~nCSO~ is reserved at location 24" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 37 " "Info: Pin ~ASDO~ is reserved at location 37" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "16 16 " "Warning: No exact pin location assignment(s) for 16 pins of 16 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEGOUT\[6\] " "Info: Pin SEGOUT\[6\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[6] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEGOUT\[5\] " "Info: Pin SEGOUT\[5\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[5] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEGOUT\[4\] " "Info: Pin SEGOUT\[4\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[4] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEGOUT\[3\] " "Info: Pin SEGOUT\[3\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[3] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEGOUT\[2\] " "Info: Pin SEGOUT\[2\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[2] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEGOUT\[1\] " "Info: Pin SEGOUT\[1\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[1] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SEGOUT\[0\] " "Info: Pin SEGOUT\[0\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SEGOUT[0] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEGOUT[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "KEY\[3\] " "Info: Pin KEY\[3\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { KEY[3] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 56 224 360 "KEY\[3..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "KEY\[2\] " "Info: Pin KEY\[2\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { KEY[2] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 56 224 360 "KEY\[3..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "KEY\[1\] " "Info: Pin KEY\[1\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { KEY[1] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 56 224 360 "KEY\[3..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "KEY\[0\] " "Info: Pin KEY\[0\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { KEY[0] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 56 224 360 "KEY\[3..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SELOUT\[2\] " "Info: Pin SELOUT\[2\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SELOUT[2] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 416 592 360 "SELOUT\[2..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SELOUT[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SELOUT\[1\] " "Info: Pin SELOUT\[1\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SELOUT[1] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 416 592 360 "SELOUT\[2..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SELOUT[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SELOUT\[0\] " "Info: Pin SELOUT\[0\] not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { SELOUT[0] } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 416 592 360 "SELOUT\[2..0\]" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { SELOUT[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLK1M " "Info: Pin CLK1M not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { CLK1M } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 448 64 232 464 "CLK1M" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK1M } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CR " "Info: Pin CR not assigned to an exact location on the device" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { CR } } } { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 392 56 224 408 "CR" "" } } } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CR } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK1M Global clock in PIN 29 " "Info: Automatically promoted signal \"CLK1M\" to use Global clock in PIN 29" {  } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 448 64 232 464 "CLK1M" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0 0}