prev_cmp_keyscan.fit.qmsg

增加有去抖模块等的fpga控制矩阵键盘的源代码及RTL级的模块图

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "7 " "Warning: Following 7 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "segout\[0\] GND " "Info: Pin segout\[0\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { segout[0] } } } { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 9 -1 0 } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { segout[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "segout\[1\] GND " "Info: Pin segout\[1\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { segout[1] } } } { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 9 -1 0 } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { segout[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "segout\[2\] GND " "Info: Pin segout\[2\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { segout[2] } } } { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 9 -1 0 } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { segout[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "segout\[3\] GND " "Info: Pin segout\[3\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { segout[3] } } } { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 9 -1 0 } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { segout[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "segout\[4\] GND " "Info: Pin segout\[4\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { segout[4] } } } { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 9 -1 0 } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { segout[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "segout\[5\] GND " "Info: Pin segout\[5\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { segout[5] } } } { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 9 -1 0 } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { segout[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "segout\[6\] GND " "Info: Pin segout\[6\] has GND driving its datain port" {  } { { "d:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus/bin/pin_planner.ppl" { segout[6] } } } { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 9 -1 0 } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { segout[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.fit.smsg " "Info: Generated suppressed messages file F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "191 " "Info: Peak virtual memory: 191 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 23 21:02:35 2009 " "Info: Processing ended: Thu Apr 23 21:02:35 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}