clk_block.vhd

增加有去抖模块等的fpga控制矩阵键盘的源代码及RTL级的模块图

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity clk_block is
port(clk_1m,clr:in std_logic;
	clk_scan:out std_logic;
	clk_key:out std_logic;
	selout:out std_logic_vector(2 downto 0));
end clk_block;

architecture one of clk_block is
signal q:std_logic_vector(10 downto 0);
begin
process(clk_1m,clr)
begin
if clr='0' then
q<=(others=>'0');
elsif clk_1m'event and clk_1m='1' then
q<=q+1;
end if;
end process;
clk_key<=q(0);
clk_scan<=q(6);
selout<=q(10 downto 8);
end one;