lcd_control.tan.rpt

用FPGA设计12832中文液晶控制器,采用状态机的方式

; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clk                          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'altera_internal_jtag~TCKUTAP'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                 ; To                                                                                                                                                                        ; From Clock                   ; To Clock                     ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 132.98 MHz ( period = 7.520 ns )                    ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:sld_hub_inst|tdo                                                                                                                                                  ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; 3.499 ns                ;
; N/A                                     ; 139.12 MHz ( period = 7.188 ns )                    ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|bypass_reg_out                                                ; sld_hub:sld_hub_inst|tdo                                                                                                                                                  ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; 3.333 ns                ;
; N/A                                     ; 140.45 MHz ( period = 7.120 ns )                    ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]                                           ; sld_hub:sld_hub_inst|tdo                                                                                                                                                  ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; 3.299 ns                ;
; N/A                                     ; 142.25 MHz ( period = 7.030 ns )                    ; sld_hub:sld_hub_inst|irf_reg[1][1]                                                                                                                                   ; sld_hub:sld_hub_inst|tdo                                                                                                                                                  ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; 3.254 ns                ;
; N/A                                     ; 143.10 MHz ( period = 6.988 ns )                    ; sld_hub:sld_hub_inst|irf_reg[1][0]                                                                                                                                   ; sld_hub:sld_hub_inst|tdo                                                                                                                                                  ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; 3.233 ns                ;
; N/A                                     ; 147.02 MHz ( period = 6.802 ns )                    ; sld_hub:sld_hub_inst|irf_reg[1][2]                                                                                                                                   ; sld_hub:sld_hub_inst|tdo                                                                                                                                                  ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; 3.140 ns                ;
; N/A                                     ; 152.88 MHz ( period = 6.541 ns )                    ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~portb_address_reg0                             ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; 5.847 ns                ;
; N/A                                     ; 152.88 MHz ( period = 6.541 ns )                    ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~portb_address_reg1                             ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; 5.847 ns                ;
; N/A                                     ; 152.88 MHz ( period = 6.541 ns )                    ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~portb_address_reg2                             ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]                                                ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; None                        ; None                      ; 5.847 ns                ;