lcd_control.tan.rpt

用FPGA设计12832中文液晶控制器,采用状态机的方式

applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack                                    ; Required Time ; Actual Time                      ; From                                                                                                                                                                 ; To                                                                                                                                                                   ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A                                      ; None          ; 3.111 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                                                         ; sld_hub:sld_hub_inst|shadow_irf_reg[1][4]                                                                                                                            ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A                                      ; None          ; 18.030 ns                        ; current_state.setbase1                                                                                                                                               ; lcd_en                                                                                                                                                               ; clk                          ; --                           ; 0            ;
; Worst-case tpd                              ; N/A                                      ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                             ; altera_reserved_tdo                                                                                                                                                  ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A                                      ; None          ; 1.707 ns                         ; altera_internal_jtag~TDIUTAP                                                                                                                                         ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[3] ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A                                      ; None          ; 132.98 MHz ( period = 7.520 ns ) ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ; sld_hub:sld_hub_inst|tdo                                                                                                                                             ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clk'                          ; N/A                                      ; None          ; 197.01 MHz ( period = 5.076 ns ) ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_datain_reg7                              ; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_memory_reg7                              ; clk                          ; clk                          ; 0            ;
; Clock Hold: 'clk'                           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; current_state.setmodel2                                                                                                                                              ; current_state.setcurs1                                                                                                                                               ; clk                          ; clk                          ; 8            ;
; Total number of failed paths                ;                                          ;               ;                                  ;                                                                                                                                                                      ;                                                                                                                                                                      ;                              ;                              ; 8            ;
+---------------------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;