lcd_control.tan.qmsg

用FPGA设计12832中文液晶控制器,采用状态机的方式

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "current_state.setmodel2 current_state.setcurs1 clk 319 ps " "Info: Found hold time violation between source  pin or register \"current_state.setmodel2\" and destination pin or register \"current_state.setcurs1\" for clock \"clk\" (Hold time is 319 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.199 ns + Largest " "Info: + Largest clock skew is 1.199 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.429 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 10.429 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns div_cnt\[0\] 2 REG LC_X8_Y14_N2 5 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y14_N2; Fanout = 5; REG Node = 'div_cnt\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk div_cnt[0] } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.570 ns) + CELL(0.590 ns) 4.595 ns Equal0~140 3 COMB LC_X8_Y14_N1 1 " "Info: 3: + IC(0.570 ns) + CELL(0.590 ns) = 4.595 ns; Loc. = LC_X8_Y14_N1; Fanout = 1; COMB Node = 'Equal0~140'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.160 ns" { div_cnt[0] Equal0~140 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.292 ns) 6.125 ns Equal0 4 COMB LC_X8_Y13_N7 9 " "Info: 4: + IC(1.238 ns) + CELL(0.292 ns) = 6.125 ns; Loc. = LC_X8_Y13_N7; Fanout = 9; COMB Node = 'Equal0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.530 ns" { Equal0~140 Equal0 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.593 ns) + CELL(0.711 ns) 10.429 ns current_state.setcurs1 5 REG LC_X1_Y25_N8 4 " "Info: 5: + IC(3.593 ns) + CELL(0.711 ns) = 10.429 ns; Loc. = LC_X1_Y25_N8; Fanout = 4; REG Node = 'current_state.setcurs1'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.304 ns" { Equal0 current_state.setcurs1 } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.997 ns ( 38.33 % ) " "Info: Total cell delay = 3.997 ns ( 38.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.432 ns ( 61.67 % ) " "Info: Total interconnect delay = 6.432 ns ( 61.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.429 ns" { clk div_cnt[0] Equal0~140 Equal0 current_state.setcurs1 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "10.429 ns" { clk {} clk~out0 {} div_cnt[0] {} Equal0~140 {} Equal0 {} current_state.setcurs1 {} } { 0.000ns 0.000ns 1.031ns 0.570ns 1.238ns 3.593ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.230 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 9.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns div_cnt\[9\] 2 REG LC_X8_Y13_N1 4 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N1; Fanout = 4; REG Node = 'div_cnt\[9\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk div_cnt[9] } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.114 ns) 4.073 ns Equal0~142 3 COMB LC_X8_Y13_N8 1 " "Info: 3: + IC(0.524 ns) + CELL(0.114 ns) = 4.073 ns; Loc. = LC_X8_Y13_N8; Fanout = 1; COMB Node = 'Equal0~142'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.638 ns" { div_cnt[9] Equal0~142 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(0.442 ns) 4.926 ns Equal0 4 COMB LC_X8_Y13_N7 9 " "Info: 4: + IC(0.411 ns) + CELL(0.442 ns) = 4.926 ns; Loc. = LC_X8_Y13_N7; Fanout = 9; COMB Node = 'Equal0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.853 ns" { Equal0~142 Equal0 } "NODE_NAME" } } { "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.593 ns) + CELL(0.711 ns) 9.230 ns current_state.setmodel2 5 REG LC_X1_Y25_N9 3 " "Info: 5: + IC(3.593 ns) + CELL(0.711 ns) = 9.230 ns; Loc. = LC_X1_Y25_N9; Fanout = 3; REG Node = 'current_state.setmodel2'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.304 ns" { Equal0 current_state.setmodel2 } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.671 ns ( 39.77 % ) " "Info: Total cell delay = 3.671 ns ( 39.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.559 ns ( 60.23 % ) " "Info: Total interconnect delay = 5.559 ns ( 60.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.230 ns" { clk div_cnt[9] Equal0~142 Equal0 current_state.setmodel2 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "9.230 ns" { clk {} clk~out0 {} div_cnt[9] {} Equal0~142 {} Equal0 {} current_state.setmodel2 {} } { 0.000ns 0.000ns 1.031ns 0.524ns 0.411ns 3.593ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.442ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.429 ns" { clk div_cnt[0] Equal0~140 Equal0 current_state.setcurs1 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "10.429 ns" { clk {} clk~out0 {} div_cnt[0] {} Equal0~140 {} Equal0 {} current_state.setcurs1 {} } { 0.000ns 0.000ns 1.031ns 0.570ns 1.238ns 3.593ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.292ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.230 ns" { clk div_cnt[9] Equal0~142 Equal0 current_state.setmodel2 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "9.230 ns" { clk {} clk~out0 {} div_cnt[9] {} Equal0~142 {} Equal0 {} current_state.setmodel2 {} } { 0.000ns 0.000ns 1.031ns 0.524ns 0.411ns 3.593ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.442ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.671 ns - Shortest register register " "Info: - Shortest register to register delay is 0.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns current_state.setmodel2 1 REG LC_X1_Y25_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y25_N9; Fanout = 3; REG Node = 'current_state.setmodel2'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { current_state.setmodel2 } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.115 ns) 0.671 ns current_state.setcurs1 2 REG LC_X1_Y25_N8 4 " "Info: 2: + IC(0.556 ns) + CELL(0.115 ns) = 0.671 ns; Loc. = LC_X1_Y25_N8; Fanout = 4; REG Node = 'current_state.setcurs1'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.671 ns" { current_state.setmodel2 current_state.setcurs1 } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.14 % ) " "Info: Total cell delay = 0.115 ns ( 17.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.556 ns ( 82.86 % ) " "Info: Total interconnect delay = 0.556 ns ( 82.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.671 ns" { current_state.setmodel2 current_state.setcurs1 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "0.671 ns" { current_state.setmodel2 {} current_state.setcurs1 {} } { 0.000ns 0.556ns } { 0.000ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.429 ns" { clk div_cnt[0] Equal0~140 Equal0 current_state.setcurs1 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "10.429 ns" { clk {} clk~out0 {} div_cnt[0] {} Equal0~140 {} Equal0 {} current_state.setcurs1 {} } { 0.000ns 0.000ns 1.031ns 0.570ns 1.238ns 3.593ns } { 0.000ns 1.469ns 0.935ns 0.590ns 0.292ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "9.230 ns" { clk div_cnt[9] Equal0~142 Equal0 current_state.setmodel2 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "9.230 ns" { clk {} clk~out0 {} div_cnt[9] {} Equal0~142 {} Equal0 {} current_state.setmodel2 {} } { 0.000ns 0.000ns 1.031ns 0.524ns 0.411ns 3.593ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.442ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.671 ns" { current_state.setmodel2 current_state.setcurs1 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "0.671 ns" { current_state.setmodel2 {} current_state.setcurs1 {} } { 0.000ns 0.556ns } { 0.000ns 0.115ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[4\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 3.111 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[4\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 3.111 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.431 ns + Longest pin register " "Info: + Longest pin to register delay is 8.431 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y13_N1 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 24; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.691 ns) + CELL(0.292 ns) 3.983 ns sld_hub:sld_hub_inst\|irf_proc~39 2 COMB LC_X31_Y19_N6 3 " "Info: 2: + IC(3.691 ns) + CELL(0.292 ns) = 3.983 ns; Loc. = LC_X31_Y19_N6; Fanout = 3; COMB Node = 'sld_hub:sld_hub_inst\|irf_proc~39'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.983 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|irf_proc~39 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.268 ns) + CELL(0.292 ns) 5.543 ns sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[0\]~265 3 COMB LC_X30_Y17_N7 1 " "Info: 3: + IC(1.268 ns) + CELL(0.292 ns) = 5.543 ns; Loc. = LC_X30_Y17_N7; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[0\]~265'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.560 ns" { sld_hub:sld_hub_inst|irf_proc~39 sld_hub:sld_hub_inst|shadow_irf_reg[1][0]~265 } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 315 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.292 ns) 6.285 ns sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[0\]~266 4 COMB LC_X30_Y17_N3 5 " "Info: 4: + IC(0.450 ns) + CELL(0.292 ns) = 6.285 ns; Loc. = LC_X30_Y17_N3; Fanout = 5; COMB Node = 'sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[0\]~266'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.742 ns" { sld_hub:sld_hub_inst|shadow_irf_reg[1][0]~265 sld_hub:sld_hub_inst|shadow_irf_reg[1][0]~266 } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 315 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.867 ns) 8.431 ns sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[4\] 5 REG LC_X31_Y18_N3 1 " "Info: 5: + IC(1.279 ns) + CELL(0.867 ns) = 8.431 ns; Loc. = LC_X31_Y18_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[4\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.146 ns" { sld_hub:sld_hub_inst|shadow_irf_reg[1][0]~266 sld_hub:sld_hub_inst|shadow_irf_reg[1][4] } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 315 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.743 ns ( 20.67 % ) " "Info: Total cell delay = 1.743 ns ( 20.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.688 ns ( 79.33 % ) " "Info: Total interconnect delay = 6.688 ns ( 79.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.431 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|irf_proc~39 sld_hub:sld_hub_inst|shadow_irf_reg[1][0]~265 sld_hub:sld_hub_inst|shadow_irf_reg[1][0]~266 sld_hub:sld_hub_inst|shadow_irf_reg[1][4] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "8.431 ns" { altera_internal_jtag~TMSUTAP {} sld_hub:sld_hub_inst|irf_proc~39 {} sld_hub:sld_hub_inst|shadow_irf_reg[1][0]~265 {} sld_hub:sld_hub_inst|shadow_irf_reg[1][0]~266 {} sld_hub:sld_hub_inst|shadow_irf_reg[1][4] {} } { 0.000ns 3.691ns 1.268ns 0.450ns 1.279ns } { 0.000ns 0.292ns 0.292ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 315 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.357 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.646 ns) + CELL(0.711 ns) 5.357 ns sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[4\] 2 REG LC_X31_Y18_N3 1 " "Info: 2: + IC(4.646 ns) + CELL(0.711 ns) = 5.357 ns; Loc. = LC_X31_Y18_N3; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|shadow_irf_reg\[1\]\[4\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.357 ns