lcd_control.tan.qmsg

用FPGA设计12832中文液晶控制器,采用状态机的方式

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|tdo 132.98 MHz 7.52 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 132.98 MHz between source register \"data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|WORD_SR\[0\]\" and destination register \"sld_hub:sld_hub_inst\|tdo\" (period= 7.52 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.499 ns + Longest register register " "Info: + Longest register to register delay is 3.499 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|WORD_SR\[0\] 1 REG LC_X29_Y17_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y17_N2; Fanout = 1; REG Node = 'data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|WORD_SR\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.292 ns) 1.512 ns data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|tdo~145 2 COMB LC_X31_Y17_N1 1 " "Info: 2: + IC(1.220 ns) + CELL(0.292 ns) = 1.512 ns; Loc. = LC_X31_Y17_N1; Fanout = 1; COMB Node = 'data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|tdo~145'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.512 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~145 } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.114 ns) 2.042 ns data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|tdo~146 3 COMB LC_X31_Y17_N3 1 " "Info: 3: + IC(0.416 ns) + CELL(0.114 ns) = 2.042 ns; Loc. = LC_X31_Y17_N3; Fanout = 1; COMB Node = 'data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|tdo~146'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.530 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~145 data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~146 } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.114 ns) 2.578 ns sld_hub:sld_hub_inst\|tdo~457 4 COMB LC_X31_Y17_N2 1 " "Info: 4: + IC(0.422 ns) + CELL(0.114 ns) = 2.578 ns; Loc. = LC_X31_Y17_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|tdo~457'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.536 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~146 sld_hub:sld_hub_inst|tdo~457 } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.478 ns) 3.499 ns sld_hub:sld_hub_inst\|tdo 5 REG LC_X31_Y17_N8 2 " "Info: 5: + IC(0.443 ns) + CELL(0.478 ns) = 3.499 ns; Loc. = LC_X31_Y17_N8; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|tdo'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.921 ns" { sld_hub:sld_hub_inst|tdo~457 sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.998 ns ( 28.52 % ) " "Info: Total cell delay = 0.998 ns ( 28.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.501 ns ( 71.48 % ) " "Info: Total interconnect delay = 2.501 ns ( 71.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.499 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~145 data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~146 sld_hub:sld_hub_inst|tdo~457 sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.499 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~145 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~146 {} sld_hub:sld_hub_inst|tdo~457 {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 1.220ns 0.416ns 0.422ns 0.443ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.355 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.644 ns) + CELL(0.711 ns) 5.355 ns sld_hub:sld_hub_inst\|tdo 2 REG LC_X31_Y17_N8 2 " "Info: 2: + IC(4.644 ns) + CELL(0.711 ns) = 5.355 ns; Loc. = LC_X31_Y17_N8; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|tdo'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.28 % ) " "Info: Total cell delay = 0.711 ns ( 13.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.644 ns ( 86.72 % ) " "Info: Total interconnect delay = 4.644 ns ( 86.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 4.644ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.355 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.355 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.644 ns) + CELL(0.711 ns) 5.355 ns data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|WORD_SR\[0\] 2 REG LC_X29_Y17_N2 1 " "Info: 2: + IC(4.644 ns) + CELL(0.711 ns) = 5.355 ns; Loc. = LC_X29_Y17_N2; Fanout = 1; REG Node = 'data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\|WORD_SR\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "d:/altera/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.28 % ) " "Info: Total cell delay = 0.711 ns ( 13.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.644 ns ( 86.72 % ) " "Info: Total interconnect delay = 4.644 ns ( 86.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] {} } { 0.000ns 4.644ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 4.644ns } { 0.000ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] {} } { 0.000ns 4.644ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "d:/altera/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "d:/altera/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } } { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.499 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~145 data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~146 sld_hub:sld_hub_inst|tdo~457 sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.499 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~145 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|tdo~146 {} sld_hub:sld_hub_inst|tdo~457 {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 1.220ns 0.416ns 0.422ns 0.443ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.478ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 4.644ns } { 0.000ns 0.711ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.355 ns" { altera_internal_jtag~TCKUTAP data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "5.355 ns" { altera_internal_jtag~TCKUTAP {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] {} } { 0.000ns 4.644ns } { 0.000ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|ram_block3a0~porta_address_reg0 memory data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|q_a\[0\] 197.01 MHz 5.076 ns Internal " "Info: Clock \"clk\" has Internal fmax of 197.01 MHz between source memory \"data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|ram_block3a0~porta_address_reg0\" and destination memory \"data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|q_a\[0\]\" (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|ram_block3a0~porta_address_reg0 1 MEM M4K_X33_Y17 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y17; Fanout = 8; MEM Node = 'data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_mg72.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mg72.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|q_a\[0\] 2 MEM M4K_X33_Y17 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X33_Y17; Fanout = 0; MEM Node = 'data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|q_a\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_mg72.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mg72.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] {} } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.184 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 3.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.708 ns) 3.184 ns data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|q_a\[0\] 2 MEM M4K_X33_Y17 0 " "Info: 2: + IC(1.007 ns) + CELL(0.708 ns) = 3.184 ns; Loc. = M4K_X33_Y17; Fanout = 0; MEM Node = 'data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|q_a\[0\]'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.715 ns" { clk data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_mg72.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mg72.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns ( 68.37 % ) " "Info: Total cell delay = 2.177 ns ( 68.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 31.63 % ) " "Info: Total interconnect delay = 1.007 ns ( 31.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.184 ns" { clk data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.184 ns" { clk {} clk~out0 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] {} } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.198 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 3.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 45 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.722 ns) 3.198 ns data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|ram_block3a0~porta_address_reg0 2 MEM M4K_X33_Y17 8 " "Info: 2: + IC(1.007 ns) + CELL(0.722 ns) = 3.198 ns; Loc. = M4K_X33_Y17; Fanout = 8; MEM Node = 'data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.729 ns" { clk data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_mg72.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mg72.tdf" 39 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns ( 68.51 % ) " "Info: Total cell delay = 2.191 ns ( 68.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 31.49 % ) " "Info: Total interconnect delay = 1.007 ns ( 31.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.198 ns" { clk data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.198 ns" { clk {} clk~out0 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 {} } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.184 ns" { clk data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.184 ns" { clk {} clk~out0 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] {} } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.708ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.198 ns" { clk data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.198 ns" { clk {} clk~out0 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 {} } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_mg72.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mg72.tdf" 39 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_mg72.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mg72.tdf" 34 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.319 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "4.319 ns" { data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] {} } { 0.000ns 0.000ns } { 0.000ns 4.319ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.184 ns" { clk data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.184 ns" { clk {} clk~out0 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|q_a[0] {} } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.708ns } "" } } { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.198 ns" { clk data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "3.198 ns" { clk {} clk~out0 {} data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ram_block3a0~porta_address_reg0 {} } { 0.000ns 0.000ns 1.007ns } { 0.000ns 1.469ns 0.722ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}