prev_cmp_lcd_control.map.qmsg

用FPGA设计12832中文液晶控制器,采用状态机的方式

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 24 10:28:11 2009 " "Info: Processing started: Fri Apr 24 10:28:11 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LCD_Control -c LCD_Control " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LCD_Control -c LCD_Control" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_Control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file LCD_Control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcd_control-one " "Info: Found design unit 1: lcd_control-one" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lcd_control " "Info: Found entity 1: lcd_control" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file data_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_rom-SYN " "Info: Found design unit 1: data_rom-SYN" {  } { { "data_rom.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/data_rom.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 data_rom " "Info: Found entity 1: data_rom" {  } { { "data_rom.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/data_rom.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_FORMAL_NOT_DECLARED" "clock LCD_Control.vhd(136) " "Error (10349): VHDL Association List error at LCD_Control.vhd(136): formal \"clock\" does not exist" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 136 0 0 } }  } 0 10349 "VHDL Association List error at %2!s!: formal \"%1!s!\" does not exist" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_FORMAL_HAS_NO_VALUE" "inclock LCD_Control.vhd(136) " "Error (10346): VHDL error at LCD_Control.vhd(136): formal port or parameter \"inclock\" must have actual or default value" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 136 0 0 } }  } 0 10346 "VHDL error at %2!s!: formal port or parameter \"%1!s!\" must have actual or default value" 0 0 "" 0 0}
{ "Error" "EVRFX_HDL_SEE_DECLARATION" "inclock LCD_Control.vhd(20) " "Error (10784): HDL error at LCD_Control.vhd(20): see declaration for object \"inclock\"" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 20 0 0 } }  } 0 10784 "HDL error at %2!s!: see declaration for object \"%1!s!\"" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "175 " "Error: Peak virtual memory: 175 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Apr 24 10:28:13 2009 " "Error: Processing ended: Fri Apr 24 10:28:13 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}