altsyncram_mp51.tdf

用FPGA设计12832中文液晶控制器,采用状态机的方式

--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone" ENABLE_RUNTIME_MOD="YES" INIT_FILE="data_rom_initfile.hex" INSTANCE_NAME="1" LOW_POWER_MODE="AUTO" NUMWORDS_A=32 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=5 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 8.1 cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ  VERSION_END


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FUNCTION altsyncram_mg72 (address_a[4..0], address_b[4..0], clock0, clock1, data_b[7..0], wren_b)
RETURNS ( q_a[7..0], q_b[7..0]);
FUNCTION sld_mod_ram_rom (data_read[7..0])
WITH ( CVALUE, IS_DATA_IN_RAM, IS_READABLE, NODE_NAME, NUMWORDS, SHIFT_COUNT_BITS, WIDTH_WORD, WIDTHAD)
RETURNS ( address[4..0], data_write[7..0], enable_write, tck_usr);

--synthesis_resources = M4K 1 sld_mod_ram_rom 1 
SUBDESIGN altsyncram_mp51
( 
	address_a[4..0]	:	input;
	clock0	:	input;
	q_a[7..0]	:	output;
) 
VARIABLE 
	altsyncram1 : altsyncram_mg72;
	mgl_prim2 : sld_mod_ram_rom
		WITH (
			CVALUE = "00000000",
			IS_DATA_IN_RAM = 1,
			IS_READABLE = 1,
			NODE_NAME = 822083584,
			NUMWORDS = 32,
			SHIFT_COUNT_BITS = 4,
			WIDTH_WORD = 8,
			WIDTHAD = 5
		);

BEGIN 
	altsyncram1.address_a[] = address_a[];
	altsyncram1.address_b[] = mgl_prim2.address[];
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = mgl_prim2.tck_usr;
	altsyncram1.data_b[] = mgl_prim2.data_write[];
	altsyncram1.wren_b = mgl_prim2.enable_write;
	mgl_prim2.data_read[] = altsyncram1.q_b[];
	q_a[] = altsyncram1.q_a[];
END;
--VALID FILE