lcd_control.map.qmsg

用FPGA设计12832中文液晶控制器,采用状态机的方式

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_mg72.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_mg72.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_mg72 " "Info: Found entity 1: altsyncram_mg72" {  } { { "db/altsyncram_mg72.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mg72.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_mg72 data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1 " "Info: Elaborating entity \"altsyncram_mg72\" for hierarchy \"data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|altsyncram_mg72:altsyncram1\"" {  } { { "db/altsyncram_mp51.tdf" "altsyncram1" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mp51.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_mp51.tdf" "mgl_prim2" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mp51.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_mp51.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mp51.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Instantiated megafunction \"data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "CVALUE 00000000 " "Info: Parameter \"CVALUE\" = \"00000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_DATA_IN_RAM 1 " "Info: Parameter \"IS_DATA_IN_RAM\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_READABLE 1 " "Info: Parameter \"IS_READABLE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_NAME 822083584 " "Info: Parameter \"NODE_NAME\" = \"822083584\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS 32 " "Info: Parameter \"NUMWORDS\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SHIFT_COUNT_BITS 4 " "Info: Parameter \"SHIFT_COUNT_BITS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_WORD 8 " "Info: Parameter \"WIDTH_WORD\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD 5 " "Info: Parameter \"WIDTHAD\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "db/altsyncram_mp51.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mp51.tdf" 35 2 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "d:/altera/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "d:/altera/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 631 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "lcd_rs GND " "Warning (13410): Pin \"lcd_rs\" is stuck at GND" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lcd_rw GND " "Warning (13410): Pin \"lcd_rw\" is stuck at GND" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 10 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lcd_data\[0\] GND " "Warning (13410): Pin \"lcd_data\[0\]\" is stuck at GND" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 12 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "lcd_data\[6\] GND " "Warning (13410): Pin \"lcd_data\[6\]\" is stuck at GND" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 12 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "current_state.wr_data1 " "Info: Register \"current_state.wr_data1\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "current_state.wr_data2 " "Info: Register \"current_state.wr_data2\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "229 " "Info: Implemented 229 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "203 " "Info: Implemented 203 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "186 " "Info: Peak virtual memory: 186 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 24 10:29:32 2009 " "Info: Processing ended: Fri Apr 24 10:29:32 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}