lcd_control.map.qmsg

用FPGA设计12832中文液晶控制器,采用状态机的方式

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 24 10:29:22 2009 " "Info: Processing started: Fri Apr 24 10:29:22 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off LCD_Control -c LCD_Control " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LCD_Control -c LCD_Control" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "LCD_Control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file LCD_Control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcd_control-one " "Info: Found design unit 1: lcd_control-one" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lcd_control " "Info: Found entity 1: lcd_control" {  } { { "LCD_Control.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_rom.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file data_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 data_rom-SYN " "Info: Found design unit 1: data_rom-SYN" {  } { { "data_rom.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/data_rom.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 data_rom " "Info: Found entity 1: data_rom" {  } { { "data_rom.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/data_rom.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "LCD_Control " "Info: Elaborating entity \"LCD_Control\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_rom data_rom:rom1 " "Info: Elaborating entity \"data_rom\" for hierarchy \"data_rom:rom1\"" {  } { { "LCD_Control.vhd" "rom1" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd" 136 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram data_rom:rom1\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"data_rom:rom1\|altsyncram:altsyncram_component\"" {  } { { "data_rom.vhd" "altsyncram_component" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/data_rom.vhd" 83 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "data_rom:rom1\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"data_rom:rom1\|altsyncram:altsyncram_component\"" {  } { { "data_rom.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/data_rom.vhd" 83 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "data_rom:rom1\|altsyncram:altsyncram_component " "Info: Instantiated megafunction \"data_rom:rom1\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file data_rom_initfile.hex " "Info: Parameter \"init_file\" = \"data_rom_initfile.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone " "Info: Parameter \"intended_device_family\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1 " "Info: Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Info: Parameter \"numwords_a\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Info: Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Info: Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Info: Parameter \"widthad_a\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 8 " "Info: Parameter \"width_a\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Info: Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "data_rom.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/data_rom.vhd" 83 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_mp51.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_mp51.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_mp51 " "Info: Found entity 1: altsyncram_mp51" {  } { { "db/altsyncram_mp51.tdf" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mp51.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_mp51 data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated " "Info: Elaborating entity \"altsyncram_mp51\" for hierarchy \"data_rom:rom1\|altsyncram:altsyncram_component\|altsyncram_mp51:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}