📄 lcd_control.map.rpt
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+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 119 ;
; Number of registers using Synchronous Clear ; 24 ;
; Number of registers using Synchronous Load ; 6 ;
; Number of registers using Asynchronous Clear ; 70 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 58 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; sld_hub:sld_hub_inst|tdo ; 2 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |lcd_control|data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |lcd_control|data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|word_counter[0] ;
; 24:1 ; 4 bits ; 64 LEs ; 36 LEs ; 28 LEs ; Yes ; |lcd_control|data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[0] ;
; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |lcd_control|sld_hub:sld_hub_inst|hub_mode_reg[2] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |lcd_control|sld_hub:sld_hub_inst|irf_reg[1][0] ;
; 5:1 ; 5 bits ; 15 LEs ; 5 LEs ; 10 LEs ; Yes ; |lcd_control|sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ;
; 6:1 ; 4 bits ; 16 LEs ; 4 LEs ; 12 LEs ; Yes ; |lcd_control|sld_hub:sld_hub_inst|irsr_reg[2] ;
; 6:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |lcd_control|sld_hub:sld_hub_inst|shadow_irf_reg[1][0] ;
; 20:1 ; 4 bits ; 52 LEs ; 32 LEs ; 20 LEs ; Yes ; |lcd_control|sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1 ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ;
+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_ROM_RECOGNITION ; OFF ; - ; - ;
+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
+-------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst ;
+------------------------------+-------+------+---------+
; Assignment ; Value ; From ; To ;
+------------------------------+-------+------+---------+
; IGNORE_LCELL_BUFFERS ; OFF ; - ; - ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF ; - ; - ;
; NOT_GATE_PUSH_BACK ; OFF ; - ; clr_reg ;
; POWER_UP_LEVEL ; LOW ; - ; clr_reg ;
+------------------------------+-------+------+---------+
+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg ;
+----------------------+-------+------+-------------------------------+
; Assignment ; Value ; From ; To ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF ; - ; - ;
+----------------------+-------+------+-------------------------------+
+--------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: data_rom:rom1|altsyncram:altsyncram_component ;
+------------------------------------+-----------------------+-------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-----------------------+-------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; WIDTH_BYTEENA ; 1 ; Untyped ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 8 ; Signed Integer ;
; WIDTHAD_A ; 5 ; Signed Integer ;
; NUMWORDS_A ; 32 ; Signed Integer ;
; OUTDATA_REG_A ; CLOCK0 ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Signed Integer ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
; INIT_FILE ; data_rom_initfile.hex ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
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