📄 lcd_control.map.rpt
字号:
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+----------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------------+
; LCD_Control.vhd ; yes ; User VHDL File ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/LCD_Control.vhd ;
; data_rom.vhd ; yes ; User Wizard-Generated File ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/data_rom.vhd ;
; altsyncram.tdf ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/lpm_decode.inc ;
; aglobal81.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/aglobal81.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Megafunction ; d:/altera/quartus/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_mp51.tdf ; yes ; Auto-Generated Megafunction ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mp51.tdf ;
; db/altsyncram_mg72.tdf ; yes ; Auto-Generated Megafunction ; F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/13液晶显示屏LCD接口设计/db/altsyncram_mg72.tdf ;
; sld_mod_ram_rom.vhd ; yes ; Encrypted Megafunction ; d:/altera/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd ;
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; d:/altera/quartus/libraries/megafunctions/sld_rom_sr.vhd ;
; sld_hub.vhd ; yes ; Encrypted Megafunction ; d:/altera/quartus/libraries/megafunctions/sld_hub.vhd ;
+----------------------------------+-----------------+------------------------------+-------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------------+
; Total logic elements ; 203 ;
; -- Combinational with no register ; 84 ;
; -- Register only ; 23 ;
; -- Combinational with a register ; 96 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 65 ;
; -- 3 input functions ; 47 ;
; -- 2 input functions ; 58 ;
; -- 1 input functions ; 7 ;
; -- 0 input functions ; 3 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 175 ;
; -- arithmetic mode ; 28 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 30 ;
; -- asynchronous clear/load mode ; 70 ;
; ; ;
; Total registers ; 119 ;
; Total logic cells in carry chains ; 33 ;
; I/O pins ; 17 ;
; Total memory bits ; 256 ;
; Maximum fan-out node ; altera_internal_jtag~TDO ;
; Maximum fan-out ; 111 ;
; Total fan-out ; 898 ;
; Average fan-out ; 3.92 ;
+---------------------------------------------+--------------------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+---------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |lcd_control ; 203 (37) ; 119 ; 256 ; 17 ; 0 ; 84 (13) ; 23 (6) ; 96 (18) ; 33 (14) ; 0 (0) ; |lcd_control ; work ;
; |data_rom:rom1| ; 58 (0) ; 32 ; 256 ; 0 ; 0 ; 26 (0) ; 4 (0) ; 28 (0) ; 14 (0) ; 0 (0) ; |lcd_control|data_rom:rom1 ; work ;
; |altsyncram:altsyncram_component| ; 58 (0) ; 32 ; 256 ; 0 ; 0 ; 26 (0) ; 4 (0) ; 28 (0) ; 14 (0) ; 0 (0) ; |lcd_control|data_rom:rom1|altsyncram:altsyncram_component ; work ;
; |altsyncram_mp51:auto_generated| ; 58 (0) ; 32 ; 256 ; 0 ; 0 ; 26 (0) ; 4 (0) ; 28 (0) ; 14 (0) ; 0 (0) ; |lcd_control|data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated ; work ;
; |altsyncram_mg72:altsyncram1| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lcd_control|data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1 ; work ;
; |sld_mod_ram_rom:mgl_prim2| ; 58 (38) ; 32 ; 0 ; 0 ; 0 ; 26 (15) ; 4 (4) ; 28 (19) ; 14 (9) ; 0 (0) ; |lcd_control|data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2 ; work ;
; |sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr| ; 20 (20) ; 9 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 9 (9) ; 5 (5) ; 0 (0) ; |lcd_control|data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ; work ;
; |sld_hub:sld_hub_inst| ; 108 (68) ; 63 ; 0 ; 0 ; 0 ; 45 (33) ; 13 (10) ; 50 (25) ; 5 (0) ; 0 (0) ; |lcd_control|sld_hub:sld_hub_inst ; work ;
; |sld_rom_sr:hub_info_reg| ; 20 (20) ; 9 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 9 (9) ; 5 (5) ; 0 (0) ; |lcd_control|sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg ; work ;
; |sld_shadow_jsm:shadow_jsm| ; 20 (20) ; 19 ; 0 ; 0 ; 0 ; 1 (1) ; 3 (3) ; 16 (16) ; 0 (0) ; 0 (0) ; |lcd_control|sld_hub:sld_hub_inst|sld_shadow_jsm:shadow_jsm ; work ;
+---------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+---------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+---------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+------+
; data_rom:rom1|altsyncram:altsyncram_component|altsyncram_mp51:auto_generated|altsyncram_mg72:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 32 ; 8 ; 32 ; 8 ; 256 ; None ;
+---------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+------+
Encoding Type: One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |lcd_control|current_state ;
+-------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-------------------------+-------------------------+------------------------+------------------------+--------------------+
; Name ; current_state.wr_data2 ; current_state.wr_data1 ; current_state.wr_addr2 ; current_state.wr_addr1 ; current_state.setcurs2 ; current_state.setcurs1 ; current_state.setmodel2 ; current_state.setmodel1 ; current_state.setbase2 ; current_state.setbase1 ; current_state.idle ;
+-------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-------------------------+-------------------------+------------------------+------------------------+--------------------+
; current_state.idle ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; current_state.setbase1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; current_state.setbase2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; current_state.setmodel1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; current_state.setmodel2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; current_state.setcurs1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; current_state.setcurs2 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; current_state.wr_addr1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; current_state.wr_addr2 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; current_state.wr_data1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; current_state.wr_data2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+-------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+------------------------+-------------------------+-------------------------+------------------------+------------------------+--------------------+
+-------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+---------------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+---------------------------------------------+
; cnt[0..4] ; Stuck at GND due to stuck port clock_enable ;
; current_state.wr_data1 ; Lost fanout ;
; current_state.wr_data2 ; Lost fanout ;
; Total Number of Removed Registers = 7 ; ;
+---------------------------------------+---------------------------------------------+
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