comp7485.vhd

来自「vhdl programs to use as a lab experiment」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity comp7485 is
port(a,b: in std_logic_vector(3 downto 0);
		rst: in std_logic;
		agb,alb,aeb: out std_logic
		);
end comp7485;
architecture reg of comp7485 is
begin
	process(a,b)
	begin
		 if (rst='1')then
		alb<='0';agb<='0';aeb<='0';
		elsif(a<b)then alb<='1';agb<='0';aeb<='0';
		elsif(a>b)then agb<='1';alb<='0';aeb<='0';
		else
		    aeb<='1';
		end if;
	end process;
end reg;